[coreboot-gerrit] [S] Change in coreboot[main]: mb/google/nissa/var/teliks: Add DP AUX BIAS connect

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83829?usp=email )

Change subject: mb/google/nissa/var/teliks: Add DP AUX BIAS connect
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mb/google/nissa/var/teliks: Add DP AUX BIAS connect

Because one side is not displayed when using type-c projection, the
configuration of DP AUX BIAS to SOC direct connection is added.

BUG=b:352263941
TEST=DP function of MB and DB workable

Change-Id: Id89d02212cdad549d1c26ed51a8d5af0f4e757c6
Signed-off-by: Qinghong Zeng 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83829
Reviewed-by: Weimin Wu 
Reviewed-by: Eric Lai 
Reviewed-by: Subrata Banik 
Tested-by: build bot (Jenkins) 
---
M src/mainboard/google/brya/variants/teliks/overridetree.cb
1 file changed, 20 insertions(+), 0 deletions(-)

Approvals:
  Eric Lai: Looks good to me, approved
  Weimin Wu: Looks good to me, but someone else must approve
  build bot (Jenkins): Verified
  Subrata Banik: Looks good to me, approved

diff --git a/src/mainboard/google/brya/variants/teliks/overridetree.cb b/src/mainboard/google/brya/variants/teliks/overridetree.cb
index 093a353..6ca555a 100644
--- a/src/mainboard/google/brya/variants/teliks/overridetree.cb
+++ b/src/mainboard/google/brya/variants/teliks/overridetree.cb
@@ -60,6 +60,26 @@
    # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39.
    register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x01515"

+	# SOC Aux orientation override:
+	# This is a bitfield that corresponds to up to 4 TCSS ports.
+	# Bits (0,1) allocated for TCSS Port1 configuration and Bits (2,3)for TCSS Port2.
+	# TcssAuxOri = 0100b
+	# Bit0 set to "0" indicates has retimer on USBC Port0, on the DB.
+	# Bit2 set to "1" indicates no retimer on USBC Port1, on the MB.
+	# Bit1,Bit3 set to "0" indicates Aux lines are not swapped on the
+	# motherboard to USBC connector
+	register "tcss_aux_ori" = "5"
+
+	register "typec_aux_bias_pads[0]" = "{
+		.pad_auxp_dc = GPP_A19,
+		.pad_auxn_dc = GPP_A20
+	}"
+
+	register "typec_aux_bias_pads[1]" = "{
+		.pad_auxp_dc = GPP_E22,
+		.pad_auxn_dc = GPP_E23
+	}"
+
    # FIVR configurations for teliks are disabled since the board doesn't have V1p05 and Vnn
    # bypass rails implemented.
    register "ext_fivr_settings" = "{