[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Correct PMC/GPIO routing information

[Lijian Zhao (Code Review)]

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/22908

Change subject: soc/intel/cannonlake: Correct PMC/GPIO routing information
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soc/intel/cannonlake: Correct PMC/GPIO routing information

PMC and GPIO DWx definition is not identical, hence update that to
correct information. For cannonlake lp PCH, GPIO group C, group E and
group GPD is different for PMC GPIO_CFG and GPIO MISCCFG.

TEST=Boot up into OS, and manually check PMC GPE status

Change-Id: I1edb83edabc72e8a762b129cf51dcd936cd37ddf
Signed-off-by: Lijian Zhao 
---
M src/soc/intel/cannonlake/gpio.c
M src/soc/intel/cannonlake/include/soc/pmc.h
2 files changed, 20 insertions(+), 9 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/22908/1

diff --git a/src/soc/intel/cannonlake/gpio.c b/src/soc/intel/cannonlake/gpio.c
index de60fa3..1227f4b 100644
--- a/src/soc/intel/cannonlake/gpio.c
+++ b/src/soc/intel/cannonlake/gpio.c
@@ -17,6 +17,7 @@
 #include <intelblocks/gpio.h>
 #include <intelblocks/pcr.h>
 #include <soc/pcr_ids.h>
+#include <soc/pmc.h>

#define CNL_GPP(s, e)				\
    {						\
@@ -160,15 +161,15 @@
 const struct pmc_to_gpio_route *soc_pmc_gpio_routes(size_t *num)
 {
    static const struct pmc_to_gpio_route routes[] = {
-		{ GPP_A, GPP_A },
-		{ GPP_B, GPP_B },
-		{ GPP_C, GPP_C },
-		{ GPP_D, GPP_D },
-		{ GPP_E, GPP_E },
-		{ GPP_F, GPP_F },
-		{ GPP_G, GPP_G },
-		{ GPP_H, GPP_H },
-		{ GPD, GPD },
+		{ PMC_GPP_A, GPP_A },
+		{ PMC_GPP_B, GPP_B },
+		{ PMC_GPP_C, GPP_C },
+		{ PMC_GPP_D, GPP_D },
+		{ PMC_GPP_E, GPP_E },
+		{ PMC_GPP_F, GPP_F },
+		{ PMC_GPP_G, GPP_G },
+		{ PMC_GPP_H, GPP_H },
+		{ PMC_GPD, GPD },
    };
    *num = ARRAY_SIZE(routes);
    return routes;
diff --git a/src/soc/intel/cannonlake/include/soc/pmc.h b/src/soc/intel/cannonlake/include/soc/pmc.h
index 0276d46..12b90d6 100644
--- a/src/soc/intel/cannonlake/include/soc/pmc.h
+++ b/src/soc/intel/cannonlake/include/soc/pmc.h
@@ -116,6 +116,16 @@
 #define  GPE0_DWX_MASK			0xf
 #define  GPE0_DW_SHIFT(x)		(4*(x))

+#define  PMC_GPP_A			0
+#define  PMC_GPP_B			1
+#define  PMC_GPP_C			0xD
+#define  PMC_GPP_D			4
+#define  PMC_GPP_E			0xE
+#define  PMC_GPP_F			5
+#define  PMC_GPP_G			2
+#define  PMC_GPP_H			6
+#define  PMC_GPD			0xA
+
 #define GBLRST_CAUSE0			0x1924
 #define   GBLRST_CAUSE0_THERMTRIP	(1 << 5)
 #define GBLRST_CAUSE1			0x1928