[coreboot-gerrit] Change in coreboot[master]: src/northbridge/amd/agesa: fix the device resource assignment

[Mike Banon (Code Review)]

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41431 )

Change subject: src/northbridge/amd/agesa: fix the device resource assignment
......................................................................

src/northbridge/amd/agesa: fix the device resource assignment

The chipset code was incorrectly adding memory resources
to the domain device after resource allocation occurred.
It's not possible to get the correct view of the address space,
and it's generally incorrect to not add resources during
read_resources(). This change fixes the order by adding resources
during read_resources().

This successfully fixes the boot problems of fam15tn A88XM-E
but fails to fix a fam16kb AM1I-A. After fam16kb will be fixed,
this change should be updated with a fix for fam14 as well.

Inspired by CB:41369.

Signed-off-by: Mike Banon 
Change-Id: I5df6d0150e777cd21f6f9a2fc776f3548da8201d
---
M src/northbridge/amd/agesa/family15tn/northbridge.c
M src/northbridge/amd/agesa/family16kb/northbridge.c
2 files changed, 12 insertions(+), 5 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/41431/1

diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c
index 9d41e7a..0194ea8 100644
--- a/src/northbridge/amd/agesa/family15tn/northbridge.c
+++ b/src/northbridge/amd/agesa/family15tn/northbridge.c
@@ -666,6 +666,8 @@
    u32 reset_memhole = 1;
 #endif

+	domain_read_resources(dev);
+
    pci_tolm = 0xffffffffUL;
    for (link = dev->link_list; link; link = link->next) {
    	pci_tolm = find_pci_tolm(link);
@@ -749,17 +751,18 @@
    }

add_uma_resource_below_tolm(dev, 7);
-
+/*
    for (link = dev->link_list; link; link = link->next) {
    	if (link->children) {
    		assign_resources(link);
    	}
    }
+*/
 }

static struct device_operations pci_domain_ops = {
-	.read_resources	  = domain_read_resources,
-	.set_resources	  = domain_set_resources,
+	.read_resources	  = domain_set_resources,
+	.set_resources	  = pci_domain_set_resources,
    .scan_bus	  = pci_domain_scan_bus,
 };

diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c
index cedc7da..0467b27 100644
--- a/src/northbridge/amd/agesa/family16kb/northbridge.c
+++ b/src/northbridge/amd/agesa/family16kb/northbridge.c
@@ -683,6 +683,8 @@
    u32 reset_memhole = 1;
 #endif

+	domain_read_resources(dev);
+
    pci_tolm = 0xffffffffUL;
    for (link = dev->link_list; link; link = link->next) {
    	pci_tolm = find_pci_tolm(link);
@@ -768,11 +770,13 @@

add_uma_resource_below_tolm(dev, 7);

+/*
    for (link = dev->link_list; link; link = link->next) {
    	if (link->children) {
    		assign_resources(link);
    	}
    }
+*/
 }

static const char *domain_acpi_name(const struct device *dev)
@@ -784,8 +788,8 @@
 }

static struct device_operations pci_domain_ops = {
-	.read_resources	  = domain_read_resources,
-	.set_resources	  = domain_set_resources,
+	.read_resources	  = domain_set_resources,
+	.set_resources	  = pci_domain_set_resources,
    .scan_bus	  = pci_domain_scan_bus,
    .acpi_name        = domain_acpi_name,
 };