Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39986 )
Change subject: soc/intel/cnl: Configure PcieRpSlotImplemented
......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39986/7//COMMIT_MSG
Commit Message:
https://review.coreboot.org/c/coreboot/+/39986/7//COMMIT_MSG@9
PS7, Line 9: Default was probably the opposite, so all devicetrees would need an
huh? probably? opposite of what?
default is 0x1 for all ports, according to fsp bsf, so yes, the devicetrees need to be updated
--
To view, visit
https://review.coreboot.org/c/coreboot/+/39986
To unsubscribe, or for help writing mail filters, visit
https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I6c57ab0ae50a37cd9a90786134e9056851a86a3c
Gerrit-Change-Number: 39986
Gerrit-PatchSet: 7
Gerrit-Owner: Felix Singer
felixsinger@posteo.net
Gerrit-Reviewer: Angel Pons
th3fanbus@gmail.com
Gerrit-Reviewer: Nico Huber
nico.h@gmx.de
Gerrit-Reviewer: Patrick Rudolph
siro@das-labor.org
Gerrit-Reviewer: build bot (Jenkins)
no-reply@coreboot.org
Gerrit-CC: Christian Walter
christian.walter@9elements.com
Gerrit-CC: Michael Niewöhner
Gerrit-CC: Paul Menzel
paulepanter@users.sourceforge.net
Gerrit-Comment-Date: Wed, 05 Aug 2020 20:57:04 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: No
Gerrit-MessageType: comment