Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62923 )
Change subject: mb/amd/chausie/devicetree: set PSPP policy to DXIO_PSPP_DISABLED ......................................................................
mb/amd/chausie/devicetree: set PSPP policy to DXIO_PSPP_DISABLED
Right now, the PSPP policy that controls if the PCIe lanes can be dynamically downgraded to a lower speed to save some power needs to be disabled in order for the link training to be successful. Once this feature is working, the PSPP policy will be switched to balanced again.
Signed-off-by: Felix Held felix-coreboot@felixheld.de Change-Id: I85a06f322c4ddff25c3a858e2b79c84b36c48932 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62923 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Fred Reitberger reitbergerfred@gmail.com Reviewed-by: Raul Rangel rrangel@chromium.org --- M src/mainboard/amd/chausie/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved Fred Reitberger: Looks good to me, but someone else must approve
diff --git a/src/mainboard/amd/chausie/devicetree.cb b/src/mainboard/amd/chausie/devicetree.cb index f3a84f3..7f37be2 100644 --- a/src/mainboard/amd/chausie/devicetree.cb +++ b/src/mainboard/amd/chausie/devicetree.cb @@ -24,7 +24,7 @@
register "s0ix_enable" = "true"
- register "pspp_policy" = "DXIO_PSPP_BALANCED" + register "pspp_policy" = "DXIO_PSPP_DISABLED" # TODO: reenable when PSPP works
device domain 0 on device ref iommu on end
1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one.