[coreboot-gerrit] Change in coreboot[master]: [TESTONLY] Generate the SPD for a LP5 test part

[Reka Norman (Code Review)]

Attention is currently required from: Reka Norman.
Hello build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/58680

to look at the new patch set (#10).

Change subject: [TESTONLY] Generate the SPD for a LP5 test part
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[TESTONLY] Generate the SPD for a LP5 test part

Add spd/lp5/memory_parts.json with a single test part.

Generate the SPD and manifests using:
util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5

The generated spd-1.hex is identical to the example SPD provided by
Intel for this part, except that the following "don't care" bytes have
been zeroed:
 - 9 Other SDRAM Optional Features
 - 16 Signal Loading
 - 19 Maximum Cycle Time
 - 20-23 CAS Latencies Supported
 - 124 Fine Offset for Maximum Cycle Time
 - 325 Module ID: Module Serial Number

Change-Id: Id96399c17577b1350c6e04c87cf40c4b2ff1478e
Signed-off-by: Reka Norman 
---
A spd/lp5/memory_parts.json
A spd/lp5/platforms_manifest.generated.txt
A spd/lp5/set-0/parts_spd_manifest.generated.txt
A spd/lp5/set-0/spd-1.hex
A spd/lp5/set-0/spd-empty.hex
5 files changed, 86 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/58680/10