Attention is currently required from: Patrick Rudolph. Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49752 )
Change subject: nb/intel/sandybridge: Use common {DMI,EP,MCH}BAR accessors ......................................................................
nb/intel/sandybridge: Use common {DMI,EP,MCH}BAR accessors
Drop unused sandybridge.h includes to avoid build failures on Ironlake.
Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 remains identical.
Change-Id: If2f0147fe50266e2fe2098cafdf004e51282f5e2 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/dell/optiplex_9010/early_init.c M src/northbridge/intel/sandybridge/Kconfig M src/northbridge/intel/sandybridge/early_init.c M src/northbridge/intel/sandybridge/memmap.h M src/northbridge/intel/sandybridge/raminit_mrc.c M src/northbridge/intel/sandybridge/sandybridge.h M src/southbridge/intel/bd82x6x/early_rcba.c M src/southbridge/intel/bd82x6x/early_usb.c M src/southbridge/intel/ibexpeak/early_usb.c 9 files changed, 22 insertions(+), 30 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/49752/1
diff --git a/src/mainboard/dell/optiplex_9010/early_init.c b/src/mainboard/dell/optiplex_9010/early_init.c index e96ee34..0b6334d 100644 --- a/src/mainboard/dell/optiplex_9010/early_init.c +++ b/src/mainboard/dell/optiplex_9010/early_init.c @@ -32,8 +32,8 @@ * FIXME: the board gets stuck in reset loop in * mainboard_romstage_entry. Avoid that by clearing SSKPD */ - pci_write_config32(HOST_BRIDGE, MCHBAR, DEFAULT_MCHBAR | 1); - pci_write_config32(HOST_BRIDGE, MCHBAR + 4, (0LL + DEFAULT_MCHBAR) >> 32); + pci_write_config32(HOST_BRIDGE, MCHBAR, CONFIG_FIXED_MCHBAR_MMIO_BASE | 1); + pci_write_config32(HOST_BRIDGE, MCHBAR + 4, 0); MCHBAR16(SSKPD_HI) = 0;
sch5545_early_init(0x2e); diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index 1388b87..277c0e2 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -151,4 +151,13 @@ config INTEL_GMA_BCLV_OFFSET default 0x48254
+config FIXED_MCHBAR_MMIO_BASE + default 0xfed10000 + +config FIXED_DMIBAR_MMIO_BASE + default 0xfed18000 + +config FIXED_EPBAR_MMIO_BASE + default 0xfed19000 + endif diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index 45b5b8f..42957e5 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -50,12 +50,12 @@ { printk(BIOS_DEBUG, "Setting up static northbridge registers..."); /* Set up all hardcoded northbridge BARs */ - pci_write_config32(HOST_BRIDGE, EPBAR, DEFAULT_EPBAR | 1); - pci_write_config32(HOST_BRIDGE, EPBAR + 4, (0LL + DEFAULT_EPBAR) >> 32); - pci_write_config32(HOST_BRIDGE, MCHBAR, DEFAULT_MCHBAR | 1); - pci_write_config32(HOST_BRIDGE, MCHBAR + 4, (0LL + DEFAULT_MCHBAR) >> 32); - pci_write_config32(HOST_BRIDGE, DMIBAR, DEFAULT_DMIBAR | 1); - pci_write_config32(HOST_BRIDGE, DMIBAR + 4, (0LL + DEFAULT_DMIBAR) >> 32); + pci_write_config32(HOST_BRIDGE, EPBAR, CONFIG_FIXED_EPBAR_MMIO_BASE | 1); + pci_write_config32(HOST_BRIDGE, EPBAR + 4, 0); + pci_write_config32(HOST_BRIDGE, MCHBAR, CONFIG_FIXED_MCHBAR_MMIO_BASE | 1); + pci_write_config32(HOST_BRIDGE, MCHBAR + 4, 0); + pci_write_config32(HOST_BRIDGE, DMIBAR, CONFIG_FIXED_DMIBAR_MMIO_BASE | 1); + pci_write_config32(HOST_BRIDGE, DMIBAR + 4, 0);
printk(BIOS_DEBUG, " done\n"); } diff --git a/src/northbridge/intel/sandybridge/memmap.h b/src/northbridge/intel/sandybridge/memmap.h index 9825125..aae0c35 100644 --- a/src/northbridge/intel/sandybridge/memmap.h +++ b/src/northbridge/intel/sandybridge/memmap.h @@ -3,11 +3,6 @@ #ifndef __NORTHBRIDGE_INTEL_SANDYBRIDGE_MEMMAP_H__ #define __NORTHBRIDGE_INTEL_SANDYBRIDGE_MEMMAP_H__
-/* Northbridge BARs */ -#define DEFAULT_MCHBAR 0xfed10000 /* 16 KB */ -#define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */ -#define DEFAULT_EPBAR 0xfed19000 /* 4 KB */ - #define GFXVT_BASE 0xfed90000ULL #define VTVC0_BASE 0xfed91000ULL
diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index eec6836..1854adb 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -308,9 +308,9 @@ { pei_data->pei_version = PEI_VERSION,
- pei_data->mchbar = (uintptr_t)DEFAULT_MCHBAR; - pei_data->dmibar = (uintptr_t)DEFAULT_DMIBAR; - pei_data->epbar = DEFAULT_EPBAR; + pei_data->mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE; + pei_data->dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE; + pei_data->epbar = CONFIG_FIXED_EPBAR_MMIO_BASE; pei_data->pciexbar = CONFIG_MMCONF_BASE_ADDRESS; pei_data->hpet_address = CONFIG_HPET_ADDRESS; pei_data->thermalbase = 0xfed08000; diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index 235ca0e..7bf7303 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -37,9 +37,8 @@ * MCHBAR */
-#define MCHBAR8(x) (*((volatile u8 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + (x)))) +#include <northbridge/intel/common/fixed_bars.h> + #define MCHBAR8_AND(x, and) (MCHBAR8(x) = MCHBAR8(x) & (and)) #define MCHBAR16_AND(x, and) (MCHBAR16(x) = MCHBAR16(x) & (and)) #define MCHBAR32_AND(x, and) (MCHBAR32(x) = MCHBAR32(x) & (and)) @@ -57,20 +56,12 @@ * EPBAR - Egress Port Root Complex Register Block */
-#define EPBAR8(x) (*((volatile u8 *)(DEFAULT_EPBAR + (x)))) -#define EPBAR16(x) (*((volatile u16 *)(DEFAULT_EPBAR + (x)))) -#define EPBAR32(x) (*((volatile u32 *)(DEFAULT_EPBAR + (x)))) - #include "registers/epbar.h"
/* * DMIBAR */
-#define DMIBAR8(x) (*((volatile u8 *)(DEFAULT_DMIBAR + (x)))) -#define DMIBAR16(x) (*((volatile u16 *)(DEFAULT_DMIBAR + (x)))) -#define DMIBAR32(x) (*((volatile u32 *)(DEFAULT_DMIBAR + (x)))) - #include "registers/dmibar.h"
#ifndef __ASSEMBLER__ diff --git a/src/southbridge/intel/bd82x6x/early_rcba.c b/src/southbridge/intel/bd82x6x/early_rcba.c index 29df6a3..49c137a 100644 --- a/src/southbridge/intel/bd82x6x/early_rcba.c +++ b/src/southbridge/intel/bd82x6x/early_rcba.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#include <northbridge/intel/sandybridge/sandybridge.h> #include "pch.h"
void southbridge_configure_default_intmap(void) diff --git a/src/southbridge/intel/bd82x6x/early_usb.c b/src/southbridge/intel/bd82x6x/early_usb.c index 8740dcf..654d44b 100644 --- a/src/southbridge/intel/bd82x6x/early_usb.c +++ b/src/southbridge/intel/bd82x6x/early_usb.c @@ -3,7 +3,6 @@ #include <device/mmio.h> #include <device/pci_ops.h> #include <device/pci_def.h> -#include <northbridge/intel/sandybridge/sandybridge.h> #include <southbridge/intel/common/rcba.h> #include <southbridge/intel/common/pmbase.h>
diff --git a/src/southbridge/intel/ibexpeak/early_usb.c b/src/southbridge/intel/ibexpeak/early_usb.c index e76ef7e..bdf711b 100644 --- a/src/southbridge/intel/ibexpeak/early_usb.c +++ b/src/southbridge/intel/ibexpeak/early_usb.c @@ -3,7 +3,6 @@ #include <device/mmio.h> #include <device/pci_ops.h> #include <device/pci_def.h> -#include <northbridge/intel/sandybridge/sandybridge.h> #include <southbridge/intel/common/rcba.h> #include <southbridge/intel/common/pmbase.h>