Vladimir Serbinenko (phcoder@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7107
-gerrit
commit eb0058b4a5443a39faef42f9cf0da61e91c145b9 Author: Vladimir Serbinenko phcoder@gmail.com Date: Fri Oct 17 15:02:18 2014 +0200
i945: Consolidate interrupt routing.
Change-Id: I1ccc8949844ddcf18ebf81781c1aa1701058b378 Signed-off-by: Vladimir Serbinenko phcoder@gmail.com --- .../apple/macbook21/acpi/i945_pci_irqs.asl | 71 ------------------ src/mainboard/apple/macbook21/devicetree.cb | 9 --- src/mainboard/apple/macbook21/romstage.c | 22 ------ src/mainboard/getac/p470/acpi/i945_pci_irqs.asl | 87 ---------------------- src/mainboard/getac/p470/devicetree.cb | 9 --- src/mainboard/getac/p470/romstage.c | 18 ----- src/mainboard/ibase/mb899/acpi/i945_pci_irqs.asl | 85 --------------------- src/mainboard/ibase/mb899/devicetree.cb | 9 --- src/mainboard/ibase/mb899/romstage.c | 18 ----- .../intel/d945gclf/acpi/i945_pci_irqs.asl | 85 --------------------- src/mainboard/intel/d945gclf/devicetree.cb | 9 --- src/mainboard/intel/d945gclf/romstage.c | 18 ----- .../kontron/986lcd-m/acpi/i945_pci_irqs.asl | 85 --------------------- src/mainboard/kontron/986lcd-m/romstage.c | 18 ----- src/mainboard/lenovo/t60/acpi/i945_pci_irqs.asl | 63 ---------------- src/mainboard/lenovo/t60/devicetree.cb | 9 --- src/mainboard/lenovo/t60/romstage.c | 22 ------ src/mainboard/lenovo/x60/acpi/i945_pci_irqs.asl | 63 ---------------- src/mainboard/lenovo/x60/devicetree.cb | 9 --- src/mainboard/lenovo/x60/romstage.c | 22 ------ src/mainboard/roda/rk886ex/acpi/i945_pci_irqs.asl | 84 --------------------- src/mainboard/roda/rk886ex/devicetree.cb | 9 --- src/mainboard/roda/rk886ex/romstage.c | 18 ----- src/northbridge/intel/i945/acpi/hostbridge.asl | 63 +++++++++++++++- src/northbridge/intel/i945/early_init.c | 26 +++++++ src/southbridge/intel/i82801gx/chip.h | 12 --- src/southbridge/intel/i82801gx/lpc.c | 28 ++++--- 27 files changed, 103 insertions(+), 868 deletions(-)
diff --git a/src/mainboard/apple/macbook21/acpi/i945_pci_irqs.asl b/src/mainboard/apple/macbook21/acpi/i945_pci_irqs.asl deleted file mode 100644 index 6047def..0000000 --- a/src/mainboard/apple/macbook21/acpi/i945_pci_irqs.asl +++ /dev/null @@ -1,71 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Sven Schnelle svens@stackframe.org - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -/* This is board specific information: IRQ routing for the - * i945 - */ - - -// PCI Interrupt Routing -Method(_PRT) -{ - If (PICM) { - Return (Package() { - Package() { 0x0001FFFF, 0, 0, 0x10 }, - Package() { 0x0002FFFF, 0, 0, 0x10 }, - Package() { 0x0007FFFF, 0, 0, 0x10 }, - Package() { 0x001BFFFF, 0, 0, 0x16 }, - Package() { 0x001CFFFF, 0, 0, 0x11 }, - Package() { 0x001CFFFF, 1, 0, 0x10 }, - Package() { 0x001CFFFF, 2, 0, 0x12 }, - Package() { 0x001CFFFF, 3, 0, 0x13 }, - Package() { 0x001DFFFF, 0, 0, 0x15 }, - Package() { 0x001DFFFF, 1, 0, 0x13 }, - Package() { 0x001DFFFF, 2, 0, 0x12 }, - Package() { 0x001DFFFF, 3, 0, 0x10 }, - Package() { 0x001EFFFF, 0, 0, 0x16 }, - Package() { 0x001EFFFF, 1, 0, 0x14 }, - Package() { 0x001FFFFF, 0, 0, 0x12 }, - Package() { 0x001FFFFF, 1, 0, 0x13 }, - Package() { 0x001FFFFF, 3, 0, 0x10 } - }) - } Else { - Return (Package() { - Package() { 0x0001FFFF, 0, _SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x0002FFFF, 0, _SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x0007FFFF, 0, _SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x001BFFFF, 0, _SB.PCI0.LPCB.LNKG, 0 }, - Package() { 0x001CFFFF, 0, _SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001CFFFF, 1, _SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x001CFFFF, 2, _SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001CFFFF, 3, _SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x001DFFFF, 0, _SB.PCI0.LPCB.LNKH, 0 }, - Package() { 0x001DFFFF, 1, _SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x001DFFFF, 2, _SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001DFFFF, 3, _SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x001EFFFF, 0, _SB.PCI0.LPCB.LNKG, 0 }, - Package() { 0x001EFFFF, 1, _SB.PCI0.LPCB.LNKE, 0 }, - Package() { 0x001FFFFF, 0, _SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001FFFFF, 1, _SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x001FFFFF, 3, _SB.PCI0.LPCB.LNKA, 0 } - }) - } -} diff --git a/src/mainboard/apple/macbook21/devicetree.cb b/src/mainboard/apple/macbook21/devicetree.cb index a3dfe3a..3104769 100644 --- a/src/mainboard/apple/macbook21/devicetree.cb +++ b/src/mainboard/apple/macbook21/devicetree.cb @@ -44,15 +44,6 @@ chip northbridge/intel/i945 subsystemid 0x17aa 0x201a end chip southbridge/intel/i82801gx - register "pirqa_routing" = "0x0b" - register "pirqb_routing" = "0x0b" - register "pirqc_routing" = "0x0b" - register "pirqd_routing" = "0x0b" - register "pirqe_routing" = "0x0b" - register "pirqf_routing" = "0x0b" - register "pirqg_routing" = "0x0b" - register "pirqh_routing" = "0x0b" - # GPI routing # 0 No effect (default) # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) diff --git a/src/mainboard/apple/macbook21/romstage.c b/src/mainboard/apple/macbook21/romstage.c index 7bec26b..d82569b 100644 --- a/src/mainboard/apple/macbook21/romstage.c +++ b/src/mainboard/apple/macbook21/romstage.c @@ -195,28 +195,6 @@ static void rcba_config(void) /* V1CAP Virtual Channel 1 Resource Capability */ RCBA32(0x001c) = 0x03128010;
- /* Device 1f interrupt pin register */ - RCBA32(0x3100) = 0x00042210; - RCBA32(0x3108) = 0x10004321; - - /* PCIe Interrupts */ - RCBA32(0x310c) = 0x00214321; - /* HD Audio Interrupt */ - RCBA32(0x3110) = 0x00000001; - - /* dev irq route register */ - RCBA16(0x3140) = 0x0232; - RCBA16(0x3142) = 0x3246; - RCBA16(0x3144) = 0x0235; - RCBA16(0x3146) = 0x3201; - RCBA16(0x3148) = 0x3216; - - /* Enable IOAPIC */ - RCBA8(0x31ff) = 0x03; - - /* Enable upper 128bytes of CMOS */ - RCBA32(0x3400) = (1 << 2); - /* Disable unused devices */ RCBA32(0x3418) = FD_PCIE6 | FD_PCIE5 | FD_PCIE4 | FD_PCIE3 | FD_INTLAN | FD_ACMOD | FD_ACAUD; RCBA32(0x3418) |= (1 << 0); // Required. diff --git a/src/mainboard/getac/p470/acpi/i945_pci_irqs.asl b/src/mainboard/getac/p470/acpi/i945_pci_irqs.asl deleted file mode 100644 index 7cd7401..0000000 --- a/src/mainboard/getac/p470/acpi/i945_pci_irqs.asl +++ /dev/null @@ -1,87 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -/* This is board specific information: IRQ routing for the - * i945 - */ - - -// PCI Interrupt Routing -Method(_PRT) -{ - If (PICM) { - Return (Package() { - // PCIe Graphics 0:1.0 - Package() { 0x0001ffff, 0, 0, 16 }, - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, 0, 16 }, - // Network - Package() { 0x0007ffff, 0, 0, 16 }, - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, 0, 22 }, - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, 0, 17 }, - Package() { 0x001cffff, 1, 0, 16 }, - Package() { 0x001cffff, 2, 0, 18 }, - Package() { 0x001cffff, 3, 0, 19 }, - // USB and EHCI 0:1d.x - Package() { 0x001dffff, 0, 0, 23 }, - Package() { 0x001dffff, 1, 0, 19 }, - Package() { 0x001dffff, 2, 0, 18 }, - Package() { 0x001dffff, 3, 0, 16 }, - // AC97 0:1e.2, 0:1e.3 - Package() { 0x001effff, 0, 0, 22 }, - Package() { 0x001effff, 1, 0, 20 }, - // LPC device 0:1f.0 - Package() { 0x001fffff, 0, 0, 18 }, - Package() { 0x001fffff, 1, 0, 19 }, - Package() { 0x001fffff, 3, 0, 16 } - }) - } Else { - Return (Package() { - // PCIe Graphics 0:1.0 - Package() { 0x0001ffff, 0, _SB.PCI0.LPCB.LNKA, 0 }, - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, _SB.PCI0.LPCB.LNKA, 0 }, - // Network 0:7.0 - Package() { 0x0007ffff, 0, _SB.PCI0.LPCB.LNKA, 0 }, - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, _SB.PCI0.LPCB.LNKG, 0 }, - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, _SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001cffff, 1, _SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x001cffff, 2, _SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001cffff, 3, _SB.PCI0.LPCB.LNKD, 0 }, - // USB and EHCI 0:1d.x - Package() { 0x001dffff, 0, _SB.PCI0.LPCB.LNKH, 0 }, - Package() { 0x001dffff, 1, _SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x001dffff, 2, _SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001dffff, 3, _SB.PCI0.LPCB.LNKA, 0 }, - // AC97 0:1e.2, 0:1e.3 - Package() { 0x001effff, 0, _SB.PCI0.LPCB.LNKG, 0 }, - Package() { 0x001effff, 1, _SB.PCI0.LPCB.LNKE, 0 }, - // LPC device 0:1f.0 - Package() { 0x001fffff, 0, _SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001fffff, 1, _SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x001fffff, 3, _SB.PCI0.LPCB.LNKA, 0 } - }) - } -} diff --git a/src/mainboard/getac/p470/devicetree.cb b/src/mainboard/getac/p470/devicetree.cb index 6256ca1..2706038 100644 --- a/src/mainboard/getac/p470/devicetree.cb +++ b/src/mainboard/getac/p470/devicetree.cb @@ -35,15 +35,6 @@ chip northbridge/intel/i945 #device pci 02.1 on end # display controller
chip southbridge/intel/i82801gx - register "pirqa_routing" = "0x0a" - register "pirqb_routing" = "0x0a" - register "pirqc_routing" = "0x0a" - register "pirqd_routing" = "0x0a" - register "pirqe_routing" = "0x80" - register "pirqf_routing" = "0x80" - register "pirqg_routing" = "0x0a" - register "pirqh_routing" = "0x0a" - # GPI routing # 0 No effect (default) # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c index ccfb076..db36605 100644 --- a/src/mainboard/getac/p470/romstage.c +++ b/src/mainboard/getac/p470/romstage.c @@ -175,24 +175,6 @@ static void rcba_config(void) //RCBA32(0x0014) = 0x80000001; //RCBA32(0x001c) = 0x03128010;
- /* Device 1f interrupt pin register */ - RCBA32(0x3100) = 0x00042220; - /* Device 1d interrupt pin register */ - RCBA32(0x310c) = 0x00214321; - - /* dev irq route register */ - RCBA16(0x3140) = 0x0232; - RCBA16(0x3142) = 0x3246; - RCBA16(0x3144) = 0x0237; - RCBA16(0x3146) = 0x3201; - RCBA16(0x3148) = 0x3216; - - /* Enable IOAPIC */ - RCBA8(0x31ff) = 0x03; - - /* Enable upper 128bytes of CMOS */ - RCBA32(0x3400) = (1 << 2); - /* Disable unused devices */ RCBA32(0x3418) = FD_PCIE6 | FD_PCIE5 | FD_INTLAN | FD_ACMOD | FD_ACAUD | FD_PATA; RCBA32(0x3418) |= (1 << 0); // Required. diff --git a/src/mainboard/ibase/mb899/acpi/i945_pci_irqs.asl b/src/mainboard/ibase/mb899/acpi/i945_pci_irqs.asl deleted file mode 100644 index 142cb80..0000000 --- a/src/mainboard/ibase/mb899/acpi/i945_pci_irqs.asl +++ /dev/null @@ -1,85 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* This is board specific information: IRQ routing for the - * i945 - */ - - -// PCI Interrupt Routing -Method(_PRT) -{ - If (PICM) { - Return (Package() { - // PCIe Graphics 0:1.0 - Package() { 0x0001ffff, 0, 0, 16 }, - Package() { 0x0001ffff, 1, 0, 17 }, - Package() { 0x0001ffff, 2, 0, 18 }, - Package() { 0x0001ffff, 3, 0, 19 }, - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, 0, 16 }, - // High Definition Audio 0:1b.0 - //Package() { 0x001bffff, 0, 0, 16 }, - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, 0, 16 }, - Package() { 0x001cffff, 1, 0, 17 }, - Package() { 0x001cffff, 2, 0, 18 }, - Package() { 0x001cffff, 3, 0, 19 }, - // USB and EHCI 0:1d.x - Package() { 0x001dffff, 0, 0, 23 }, - Package() { 0x001dffff, 1, 0, 19 }, - Package() { 0x001dffff, 2, 0, 18 }, - Package() { 0x001dffff, 3, 0, 16 }, - // AC97/IDE 0:1e.2, 0:1e.3 - Package() { 0x001effff, 0, 0, 17 }, - Package() { 0x001effff, 1, 0, 20 }, - // LPC device 0:1f.0 - Package() { 0x001fffff, 0, 0, 18 }, - Package() { 0x001fffff, 1, 0, 19}, - }) - } Else { - Return (Package() { - // PCIe Graphics 0:1.0 - Package() { 0x0001ffff, 0, _SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x0001ffff, 1, _SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x0001ffff, 2, _SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x0001ffff, 3, _SB.PCI0.LPCB.LNKD, 0 }, - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, _SB.PCI0.LPCB.LNKA, 0 }, - // High Definition Audio 0:1b.0 - //Package() { 0x001bffff, 0, _SB.PCI0.LPCB.LNKA, 0 }, - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, _SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x001cffff, 1, _SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001cffff, 2, _SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001cffff, 3, _SB.PCI0.LPCB.LNKD, 0 }, - // USB and EHCI 0:1d.x - Package() { 0x001dffff, 0, _SB.PCI0.LPCB.LNKH, 0 }, - Package() { 0x001dffff, 1, _SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x001dffff, 2, _SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001dffff, 3, _SB.PCI0.LPCB.LNKA, 0 }, - // AC97/IDE 0:1e.2, 0:1e.3 - Package() { 0x001effff, 0, _SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001effff, 1, _SB.PCI0.LPCB.LNKE, 0 }, - // LPC device 0:1f.0 - Package() { 0x001fffff, 0, _SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001fffff, 1, _SB.PCI0.LPCB.LNKD, 0 }, - }) - } -} diff --git a/src/mainboard/ibase/mb899/devicetree.cb b/src/mainboard/ibase/mb899/devicetree.cb index c304908..6a6ced8 100644 --- a/src/mainboard/ibase/mb899/devicetree.cb +++ b/src/mainboard/ibase/mb899/devicetree.cb @@ -12,15 +12,6 @@ chip northbridge/intel/i945 device pci 02.1 on end # display controller
chip southbridge/intel/i82801gx - register "pirqa_routing" = "0x05" - register "pirqb_routing" = "0x07" - register "pirqc_routing" = "0x05" - register "pirqd_routing" = "0x07" - register "pirqe_routing" = "0x80" - register "pirqf_routing" = "0x80" - register "pirqg_routing" = "0x80" - register "pirqh_routing" = "0x06" - # GPI routing # 0 No effect (default) # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c index 2a81921..8f13504 100644 --- a/src/mainboard/ibase/mb899/romstage.c +++ b/src/mainboard/ibase/mb899/romstage.c @@ -147,24 +147,6 @@ static void rcba_config(void) //RCBA32(0x0014) = 0x80000001; //RCBA32(0x001c) = 0x03128010;
- /* Device 1f interrupt pin register */ - RCBA32(0x3100) = 0x00042210; - /* Device 1d interrupt pin register */ - RCBA32(0x310c) = 0x00214321; - - /* dev irq route register */ - RCBA16(0x3140) = 0x0132; - RCBA16(0x3142) = 0x0146; - RCBA16(0x3144) = 0x0237; - RCBA16(0x3146) = 0x3201; - RCBA16(0x3148) = 0x0146; - - /* Enable IOAPIC */ - RCBA8(0x31ff) = 0x03; - - /* Enable upper 128bytes of CMOS */ - RCBA32(0x3400) = (1 << 2); - /* Enable PCIe Root Port Clock Gate */ // RCBA32(0x341c) = 0x00000001; } diff --git a/src/mainboard/intel/d945gclf/acpi/i945_pci_irqs.asl b/src/mainboard/intel/d945gclf/acpi/i945_pci_irqs.asl deleted file mode 100644 index aa85527..0000000 --- a/src/mainboard/intel/d945gclf/acpi/i945_pci_irqs.asl +++ /dev/null @@ -1,85 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* This is board specific information: IRQ routing for the - * i945 - */ - - -// PCI Interrupt Routing -Method(_PRT) -{ - If (PICM) { - Return (Package() { - // PCIe Graphics 0:1.0 - Package() { 0x0001ffff, 0, 0, 16 }, - Package() { 0x0001ffff, 1, 0, 17 }, - Package() { 0x0001ffff, 2, 0, 18 }, - Package() { 0x0001ffff, 3, 0, 19 }, - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, 0, 16 }, - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, 0, 22 }, - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, 0, 17 }, - Package() { 0x001cffff, 1, 0, 16 }, - Package() { 0x001cffff, 2, 0, 18 }, - Package() { 0x001cffff, 3, 0, 19 }, - // USB and EHCI 0:1d.x - Package() { 0x001dffff, 0, 0, 23 }, - Package() { 0x001dffff, 1, 0, 19 }, - Package() { 0x001dffff, 2, 0, 18 }, - Package() { 0x001dffff, 3, 0, 16 }, - // AC97 0:1e.2, 0:1e.3 - Package() { 0x001effff, 0, 0, 22 }, - Package() { 0x001effff, 1, 0, 20 }, - // LPC device 0:1f.0 - Package() { 0x001fffff, 0, 0, 18 }, - Package() { 0x001fffff, 1, 0, 19 }, - }) - } Else { - Return (Package() { - // PCIe Graphics 0:1.0 - Package() { 0x0001ffff, 0, _SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x0001ffff, 1, _SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x0001ffff, 2, _SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x0001ffff, 3, _SB.PCI0.LPCB.LNKD, 0 }, - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, _SB.PCI0.LPCB.LNKA, 0 }, - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, _SB.PCI0.LPCB.LNKF, 0 }, - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, _SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001cffff, 1, _SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x001cffff, 2, _SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001cffff, 3, _SB.PCI0.LPCB.LNKD, 0 }, - // USB and EHCI 0:1d.x - Package() { 0x001dffff, 0, _SB.PCI0.LPCB.LNKH, 0 }, - Package() { 0x001dffff, 1, _SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x001dffff, 2, _SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001dffff, 3, _SB.PCI0.LPCB.LNKA, 0 }, - // AC97 0:1e.2, 0:1e.3 - Package() { 0x001effff, 0, _SB.PCI0.LPCB.LNKG, 0 }, - Package() { 0x001effff, 1, _SB.PCI0.LPCB.LNKE, 0 }, - // LPC device 0:1f.0 - Package() { 0x001fffff, 0, _SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001fffff, 1, _SB.PCI0.LPCB.LNKD, 0 }, - }) - } -} diff --git a/src/mainboard/intel/d945gclf/devicetree.cb b/src/mainboard/intel/d945gclf/devicetree.cb index d389d8a..96a0f45 100644 --- a/src/mainboard/intel/d945gclf/devicetree.cb +++ b/src/mainboard/intel/d945gclf/devicetree.cb @@ -33,15 +33,6 @@ chip northbridge/intel/i945 device pci 02.1 on end # display controller
chip southbridge/intel/i82801gx - register "pirqa_routing" = "0x05" - register "pirqb_routing" = "0x07" - register "pirqc_routing" = "0x05" - register "pirqd_routing" = "0x07" - register "pirqe_routing" = "0x80" - register "pirqf_routing" = "0x80" - register "pirqg_routing" = "0x80" - register "pirqh_routing" = "0x06" - # GPI routing # 0 No effect (default) # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c index 4508968..f8fc155 100644 --- a/src/mainboard/intel/d945gclf/romstage.c +++ b/src/mainboard/intel/d945gclf/romstage.c @@ -74,24 +74,6 @@ static void rcba_config(void) //RCBA32(0x0014) = 0x80000001; //RCBA32(0x001c) = 0x03128010;
- /* Device 1f interrupt pin register */ - RCBA32(0x3100) = 0x00042210; - /* Device 1d interrupt pin register */ - RCBA32(0x310c) = 0x00214321; - - /* dev irq route register */ - RCBA16(0x3140) = 0x0132; - RCBA16(0x3142) = 0x0146; - RCBA16(0x3144) = 0x0237; - RCBA16(0x3146) = 0x3201; - RCBA16(0x3148) = 0x0146; - - /* Enable IOAPIC */ - RCBA8(0x31ff) = 0x03; - - /* Enable upper 128bytes of CMOS */ - RCBA32(0x3400) = (1 << 2); - /* Disable unused devices */ //RCBA32(0x3418) = FD_PCIE6|FD_PCIE5|FD_PCIE4|FD_ACMOD|FD_ACAUD|FD_PATA; // RCBA32(0x3418) |= (1 << 0); // Required. diff --git a/src/mainboard/kontron/986lcd-m/acpi/i945_pci_irqs.asl b/src/mainboard/kontron/986lcd-m/acpi/i945_pci_irqs.asl deleted file mode 100644 index cd1fed5..0000000 --- a/src/mainboard/kontron/986lcd-m/acpi/i945_pci_irqs.asl +++ /dev/null @@ -1,85 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* This is board specific information: IRQ routing for the - * i945 - */ - - -// PCI Interrupt Routing -Method(_PRT) -{ - If (PICM) { - Return (Package() { - // PCIe Graphics 0:1.0 - Package() { 0x0001ffff, 0, 0, 16 }, - Package() { 0x0001ffff, 1, 0, 17 }, - Package() { 0x0001ffff, 2, 0, 18 }, - Package() { 0x0001ffff, 3, 0, 19 }, - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, 0, 16 }, - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, 0, 16 }, - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, 0, 16 }, - Package() { 0x001cffff, 1, 0, 17 }, - Package() { 0x001cffff, 2, 0, 18 }, - Package() { 0x001cffff, 3, 0, 19 }, - // USB and EHCI 0:1d.x - Package() { 0x001dffff, 0, 0, 23 }, - Package() { 0x001dffff, 1, 0, 19 }, - Package() { 0x001dffff, 2, 0, 18 }, - Package() { 0x001dffff, 3, 0, 16 }, - // AC97/IDE 0:1e.2, 0:1e.3 - Package() { 0x001effff, 0, 0, 17 }, - Package() { 0x001effff, 1, 0, 20 }, - // LPC device 0:1f.0 - Package() { 0x001fffff, 0, 0, 18 }, - Package() { 0x001fffff, 1, 0, 19}, - }) - } Else { - Return (Package() { - // PCIe Graphics 0:1.0 - Package() { 0x0001ffff, 0, _SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x0001ffff, 1, _SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x0001ffff, 2, _SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x0001ffff, 3, _SB.PCI0.LPCB.LNKD, 0 }, - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, _SB.PCI0.LPCB.LNKA, 0 }, - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, _SB.PCI0.LPCB.LNKA, 0 }, - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, _SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x001cffff, 1, _SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001cffff, 2, _SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001cffff, 3, _SB.PCI0.LPCB.LNKD, 0 }, - // USB and EHCI 0:1d.x - Package() { 0x001dffff, 0, _SB.PCI0.LPCB.LNKH, 0 }, - Package() { 0x001dffff, 1, _SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x001dffff, 2, _SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001dffff, 3, _SB.PCI0.LPCB.LNKA, 0 }, - // AC97/IDE 0:1e.2, 0:1e.3 - Package() { 0x001effff, 0, _SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001effff, 1, _SB.PCI0.LPCB.LNKE, 0 }, - // LPC device 0:1f.0 - Package() { 0x001fffff, 0, _SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001fffff, 1, _SB.PCI0.LPCB.LNKD, 0 }, - }) - } -} diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c index 2c89e6c..8b9e6f2 100644 --- a/src/mainboard/kontron/986lcd-m/romstage.c +++ b/src/mainboard/kontron/986lcd-m/romstage.c @@ -206,24 +206,6 @@ static void rcba_config(void) //RCBA32(0x0014) = 0x80000001; //RCBA32(0x001c) = 0x03128010;
- /* Device 1f interrupt pin register */ - RCBA32(0x3100) = 0x00042210; - /* Device 1d interrupt pin register */ - RCBA32(0x310c) = 0x00214321; - - /* dev irq route register */ - RCBA16(0x3140) = 0x0132; - RCBA16(0x3142) = 0x3241; - RCBA16(0x3144) = 0x0237; - RCBA16(0x3146) = 0x3210; - RCBA16(0x3148) = 0x3210; - - /* Enable IOAPIC */ - RCBA8(0x31ff) = 0x03; - - /* Enable upper 128bytes of CMOS */ - RCBA32(0x3400) = (1 << 2); - /* Now, this is a bit ugly. As per PCI specification, function 0 of a * device always has to be implemented. So disabling ethernet port 1 * would essentially disable all three ethernet ports of the mainboard. diff --git a/src/mainboard/lenovo/t60/acpi/i945_pci_irqs.asl b/src/mainboard/lenovo/t60/acpi/i945_pci_irqs.asl deleted file mode 100644 index e834ae1..0000000 --- a/src/mainboard/lenovo/t60/acpi/i945_pci_irqs.asl +++ /dev/null @@ -1,63 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Sven Schnelle svens@stackframe.org - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -/* This is board specific information: IRQ routing for the - * i945 - */ - - -// PCI Interrupt Routing -Method(_PRT) -{ - If (PICM) { - Return (Package() { - Package() { 0x0002ffff, 0, 0, 0x10 }, // VGA - Package() { 0x001bffff, 1, 0, 0x11 }, // Audio - Package() { 0x001cffff, 0, 0, 0x14 }, // PCI bridge - Package() { 0x001cffff, 1, 0, 0x15 }, // PCI bridge - Package() { 0x001cffff, 2, 0, 0x16 }, // PCI bridge - Package() { 0x001cffff, 3, 0, 0x17 }, // PCI bridge - Package() { 0x001dffff, 0, 0, 0x10 }, // USB - Package() { 0x001dffff, 1, 0, 0x11 }, // USB - Package() { 0x001dffff, 2, 0, 0x12 }, // USB - Package() { 0x001dffff, 3, 0, 0x13 }, // USB - Package() { 0x001fffff, 0, 0, 0x17 }, // LPC - Package() { 0x001fffff, 1, 0, 0x10 }, // IDE - Package() { 0x001fffff, 2, 0, 0x10 } // SATA - }) - } Else { - Return (Package() { - Package() { 0x0002ffff, 0, _SB.PCI0.LPCB.LNKA, 0 }, // VGA - Package() { 0x001bffff, 1, _SB.PCI0.LPCB.LNKB, 0 }, // Audio - Package() { 0x001cffff, 0, _SB.PCI0.LPCB.LNKE, 0 }, // PCI - Package() { 0x001cffff, 1, _SB.PCI0.LPCB.LNKF, 0 }, // PCI - Package() { 0x001cffff, 2, _SB.PCI0.LPCB.LNKG, 0 }, // PCI - Package() { 0x001cffff, 3, _SB.PCI0.LPCB.LNKH, 0 }, // PCI - Package() { 0x001dffff, 0, _SB.PCI0.LPCB.LNKA, 0 }, // USB - Package() { 0x001dffff, 1, _SB.PCI0.LPCB.LNKB, 0 }, // USB - Package() { 0x001dffff, 2, _SB.PCI0.LPCB.LNKC, 0 }, // USB - Package() { 0x001dffff, 3, _SB.PCI0.LPCB.LNKD, 0 }, // USB - Package() { 0x001fffff, 0, _SB.PCI0.LPCB.LNKH, 0 }, // LPC - Package() { 0x001fffff, 1, _SB.PCI0.LPCB.LNKA, 0 }, // IDE - Package() { 0x001fffff, 2, _SB.PCI0.LPCB.LNKA, 0 } // SATA - }) - } -} diff --git a/src/mainboard/lenovo/t60/devicetree.cb b/src/mainboard/lenovo/t60/devicetree.cb index f092380..7370b45 100644 --- a/src/mainboard/lenovo/t60/devicetree.cb +++ b/src/mainboard/lenovo/t60/devicetree.cb @@ -46,15 +46,6 @@ chip northbridge/intel/i945 end
chip southbridge/intel/i82801gx - register "pirqa_routing" = "0x0b" - register "pirqb_routing" = "0x0b" - register "pirqc_routing" = "0x0b" - register "pirqd_routing" = "0x0b" - register "pirqe_routing" = "0x0b" - register "pirqf_routing" = "0x0b" - register "pirqg_routing" = "0x0b" - register "pirqh_routing" = "0x0b" - # GPI routing # 0 No effect (default) # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c index f0ebcbc..1406c8f 100644 --- a/src/mainboard/lenovo/t60/romstage.c +++ b/src/mainboard/lenovo/t60/romstage.c @@ -117,28 +117,6 @@ static void rcba_config(void) RCBA32(0x0014) = 0x80000001; RCBA32(0x001c) = 0x03128010;
- /* Device 1f interrupt pin register */ - RCBA32(0x3100) = 0x00001230; - RCBA32(0x3108) = 0x40004321; - - /* PCIe Interrupts */ - RCBA32(0x310c) = 0x00004321; - /* HD Audio Interrupt */ - RCBA32(0x3110) = 0x00000002; - - /* dev irq route register */ - RCBA16(0x3140) = 0x1007; - RCBA16(0x3142) = 0x0076; - RCBA16(0x3144) = 0x3210; - RCBA16(0x3146) = 0x7654; - RCBA16(0x3148) = 0x0010; - - /* Enable IOAPIC */ - RCBA8(0x31ff) = 0x03; - - /* Enable upper 128bytes of CMOS */ - RCBA32(0x3400) = (1 << 2); - /* Disable unused devices */ RCBA32(0x3418) = FD_PCIE6 | FD_PCIE5 | FD_INTLAN | FD_ACMOD | FD_ACAUD; RCBA32(0x3418) |= (1 << 0); // Required. diff --git a/src/mainboard/lenovo/x60/acpi/i945_pci_irqs.asl b/src/mainboard/lenovo/x60/acpi/i945_pci_irqs.asl deleted file mode 100644 index e834ae1..0000000 --- a/src/mainboard/lenovo/x60/acpi/i945_pci_irqs.asl +++ /dev/null @@ -1,63 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Sven Schnelle svens@stackframe.org - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -/* This is board specific information: IRQ routing for the - * i945 - */ - - -// PCI Interrupt Routing -Method(_PRT) -{ - If (PICM) { - Return (Package() { - Package() { 0x0002ffff, 0, 0, 0x10 }, // VGA - Package() { 0x001bffff, 1, 0, 0x11 }, // Audio - Package() { 0x001cffff, 0, 0, 0x14 }, // PCI bridge - Package() { 0x001cffff, 1, 0, 0x15 }, // PCI bridge - Package() { 0x001cffff, 2, 0, 0x16 }, // PCI bridge - Package() { 0x001cffff, 3, 0, 0x17 }, // PCI bridge - Package() { 0x001dffff, 0, 0, 0x10 }, // USB - Package() { 0x001dffff, 1, 0, 0x11 }, // USB - Package() { 0x001dffff, 2, 0, 0x12 }, // USB - Package() { 0x001dffff, 3, 0, 0x13 }, // USB - Package() { 0x001fffff, 0, 0, 0x17 }, // LPC - Package() { 0x001fffff, 1, 0, 0x10 }, // IDE - Package() { 0x001fffff, 2, 0, 0x10 } // SATA - }) - } Else { - Return (Package() { - Package() { 0x0002ffff, 0, _SB.PCI0.LPCB.LNKA, 0 }, // VGA - Package() { 0x001bffff, 1, _SB.PCI0.LPCB.LNKB, 0 }, // Audio - Package() { 0x001cffff, 0, _SB.PCI0.LPCB.LNKE, 0 }, // PCI - Package() { 0x001cffff, 1, _SB.PCI0.LPCB.LNKF, 0 }, // PCI - Package() { 0x001cffff, 2, _SB.PCI0.LPCB.LNKG, 0 }, // PCI - Package() { 0x001cffff, 3, _SB.PCI0.LPCB.LNKH, 0 }, // PCI - Package() { 0x001dffff, 0, _SB.PCI0.LPCB.LNKA, 0 }, // USB - Package() { 0x001dffff, 1, _SB.PCI0.LPCB.LNKB, 0 }, // USB - Package() { 0x001dffff, 2, _SB.PCI0.LPCB.LNKC, 0 }, // USB - Package() { 0x001dffff, 3, _SB.PCI0.LPCB.LNKD, 0 }, // USB - Package() { 0x001fffff, 0, _SB.PCI0.LPCB.LNKH, 0 }, // LPC - Package() { 0x001fffff, 1, _SB.PCI0.LPCB.LNKA, 0 }, // IDE - Package() { 0x001fffff, 2, _SB.PCI0.LPCB.LNKA, 0 } // SATA - }) - } -} diff --git a/src/mainboard/lenovo/x60/devicetree.cb b/src/mainboard/lenovo/x60/devicetree.cb index fcf7c29..b9f181e 100644 --- a/src/mainboard/lenovo/x60/devicetree.cb +++ b/src/mainboard/lenovo/x60/devicetree.cb @@ -44,15 +44,6 @@ chip northbridge/intel/i945 subsystemid 0x17aa 0x201a end chip southbridge/intel/i82801gx - register "pirqa_routing" = "0x0b" - register "pirqb_routing" = "0x0b" - register "pirqc_routing" = "0x0b" - register "pirqd_routing" = "0x0b" - register "pirqe_routing" = "0x0b" - register "pirqf_routing" = "0x0b" - register "pirqg_routing" = "0x0b" - register "pirqh_routing" = "0x0b" - # GPI routing # 0 No effect (default) # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c index 1310b33..1201f30 100644 --- a/src/mainboard/lenovo/x60/romstage.c +++ b/src/mainboard/lenovo/x60/romstage.c @@ -124,28 +124,6 @@ static void rcba_config(void) RCBA32(0x0014) = 0x80000001; RCBA32(0x001c) = 0x03128010;
- /* Device 1f interrupt pin register */ - RCBA32(0x3100) = 0x00001230; - RCBA32(0x3108) = 0x40004321; - - /* PCIe Interrupts */ - RCBA32(0x310c) = 0x00004321; - /* HD Audio Interrupt */ - RCBA32(0x3110) = 0x00000002; - - /* dev irq route register */ - RCBA16(0x3140) = 0x1007; - RCBA16(0x3142) = 0x0076; - RCBA16(0x3144) = 0x3210; - RCBA16(0x3146) = 0x7654; - RCBA16(0x3148) = 0x0010; - - /* Enable IOAPIC */ - RCBA8(0x31ff) = 0x03; - - /* Enable upper 128bytes of CMOS */ - RCBA32(0x3400) = (1 << 2); - /* Disable unused devices */ RCBA32(0x3418) = FD_PCIE6 | FD_PCIE5 | FD_INTLAN | FD_ACMOD | FD_ACAUD; RCBA32(0x3418) |= (1 << 0); // Required. diff --git a/src/mainboard/roda/rk886ex/acpi/i945_pci_irqs.asl b/src/mainboard/roda/rk886ex/acpi/i945_pci_irqs.asl deleted file mode 100644 index 118319c..0000000 --- a/src/mainboard/roda/rk886ex/acpi/i945_pci_irqs.asl +++ /dev/null @@ -1,84 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -/* This is board specific information: IRQ routing for the - * i945 - */ - - -// PCI Interrupt Routing -Method(_PRT) -{ - If (PICM) { - Return (Package() { - // PCIe Graphics 0:1.0 - Package() { 0x0001ffff, 0, 0, 16 }, - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, 0, 16 }, - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, 0, 22 }, - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, 0, 17 }, - Package() { 0x001cffff, 1, 0, 16 }, - Package() { 0x001cffff, 2, 0, 18 }, - Package() { 0x001cffff, 3, 0, 19 }, - // USB and EHCI 0:1d.x - Package() { 0x001dffff, 0, 0, 23 }, - Package() { 0x001dffff, 1, 0, 19 }, - Package() { 0x001dffff, 2, 0, 18 }, - Package() { 0x001dffff, 3, 0, 16 }, - // AC97 0:1e.2, 0:1e.3 - Package() { 0x001effff, 0, 0, 22 }, - Package() { 0x001effff, 1, 0, 20 }, - // LPC device 0:1f.0 - Package() { 0x001fffff, 0, 0, 18 }, - Package() { 0x001fffff, 1, 0, 19 }, - Package() { 0x001fffff, 1, 0, 20 }, - Package() { 0x001fffff, 3, 0, 16 } - }) - } Else { - Return (Package() { - // PCIe Graphics 0:1.0 - Package() { 0x0001ffff, 0, _SB.PCI0.LPCB.LNKA, 0 }, - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, _SB.PCI0.LPCB.LNKA, 0 }, - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, _SB.PCI0.LPCB.LNKG, 0 }, - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, _SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001cffff, 1, _SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x001cffff, 2, _SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001cffff, 3, _SB.PCI0.LPCB.LNKD, 0 }, - // USB and EHCI 0:1d.x - Package() { 0x001dffff, 0, _SB.PCI0.LPCB.LNKH, 0 }, - Package() { 0x001dffff, 1, _SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x001dffff, 2, _SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001dffff, 3, _SB.PCI0.LPCB.LNKA, 0 }, - // AC97 0:1e.2, 0:1e.3 - Package() { 0x001effff, 0, _SB.PCI0.LPCB.LNKG, 0 }, - Package() { 0x001effff, 1, _SB.PCI0.LPCB.LNKE, 0 }, - // LPC device 0:1f.0 - Package() { 0x001fffff, 0, _SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001fffff, 1, _SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x001fffff, 3, _SB.PCI0.LPCB.LNKA, 0 } - }) - } -} diff --git a/src/mainboard/roda/rk886ex/devicetree.cb b/src/mainboard/roda/rk886ex/devicetree.cb index 7b9d7a1..8da6a3f 100644 --- a/src/mainboard/roda/rk886ex/devicetree.cb +++ b/src/mainboard/roda/rk886ex/devicetree.cb @@ -36,15 +36,6 @@ chip northbridge/intel/i945 device pci 02.1 on end # display controller
chip southbridge/intel/i82801gx - register "pirqa_routing" = "0x0b" - register "pirqb_routing" = "0x0b" - register "pirqc_routing" = "0x0b" - register "pirqd_routing" = "0x0b" - register "pirqe_routing" = "0x80" - register "pirqf_routing" = "0x80" - register "pirqg_routing" = "0x0b" - register "pirqh_routing" = "0x0b" - # GPI routing # 0 No effect (default) # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c index 071fa2a..8ef3b02 100644 --- a/src/mainboard/roda/rk886ex/romstage.c +++ b/src/mainboard/roda/rk886ex/romstage.c @@ -153,24 +153,6 @@ static void rcba_config(void) //RCBA32(0x0014) = 0x80000001; //RCBA32(0x001c) = 0x03128010;
- /* Device 1f interrupt pin register */ - RCBA32(0x3100) = 0x00042220; - /* Device 1d interrupt pin register */ - RCBA32(0x310c) = 0x00214321; - - /* dev irq route register */ - RCBA16(0x3140) = 0x0232; - RCBA16(0x3142) = 0x3246; - RCBA16(0x3144) = 0x0237; - RCBA16(0x3146) = 0x3201; - RCBA16(0x3148) = 0x3216; - - /* Enable IOAPIC */ - RCBA8(0x31ff) = 0x03; - - /* Enable upper 128bytes of CMOS */ - RCBA32(0x3400) = (1 << 2); - /* Disable unused devices */ RCBA32(0x3418) = FD_PCIE6 | FD_PCIE5 | FD_PCIE3 | FD_PCIE2 | FD_INTLAN | FD_ACMOD | FD_HDAUD | FD_PATA; diff --git a/src/northbridge/intel/i945/acpi/hostbridge.asl b/src/northbridge/intel/i945/acpi/hostbridge.asl index df81689..df34bc4 100644 --- a/src/northbridge/intel/i945/acpi/hostbridge.asl +++ b/src/northbridge/intel/i945/acpi/hostbridge.asl @@ -235,5 +235,64 @@ Method (_CRS, 0, Serialized) Return (MCRS) }
-/* IRQ assignment is mainboard specific. Get it from mainboard ACPI code */ -#include "acpi/i945_pci_irqs.asl" +// PCI Interrupt Routing +Method(_PRT) +{ + If (PICM) { + Return (Package() { + // PCIe Graphics 0:1.0 + Package() { 0x0001ffff, 0, 0, 16 }, + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, 0, 16 }, + // Network + Package() { 0x0007ffff, 0, 0, 16 }, + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, 0, 22 }, + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, 0, 17 }, + Package() { 0x001cffff, 1, 0, 16 }, + Package() { 0x001cffff, 2, 0, 18 }, + Package() { 0x001cffff, 3, 0, 19 }, + // USB and EHCI 0:1d.x + Package() { 0x001dffff, 0, 0, 23 }, + Package() { 0x001dffff, 1, 0, 19 }, + Package() { 0x001dffff, 2, 0, 18 }, + Package() { 0x001dffff, 3, 0, 16 }, + // AC97 0:1e.2, 0:1e.3 + Package() { 0x001effff, 0, 0, 22 }, + Package() { 0x001effff, 1, 0, 20 }, + // LPC device 0:1f.0 + Package() { 0x001fffff, 0, 0, 18 }, + Package() { 0x001fffff, 1, 0, 19 }, + Package() { 0x001fffff, 3, 0, 16 } + }) + } Else { + Return (Package() { + // PCIe Graphics 0:1.0 + Package() { 0x0001ffff, 0, _SB.PCI0.LPCB.LNKA, 0 }, + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, _SB.PCI0.LPCB.LNKA, 0 }, + // Network 0:7.0 + Package() { 0x0007ffff, 0, _SB.PCI0.LPCB.LNKA, 0 }, + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, _SB.PCI0.LPCB.LNKG, 0 }, + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, _SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001cffff, 1, _SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x001cffff, 2, _SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001cffff, 3, _SB.PCI0.LPCB.LNKD, 0 }, + // USB and EHCI 0:1d.x + Package() { 0x001dffff, 0, _SB.PCI0.LPCB.LNKH, 0 }, + Package() { 0x001dffff, 1, _SB.PCI0.LPCB.LNKD, 0 }, + Package() { 0x001dffff, 2, _SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001dffff, 3, _SB.PCI0.LPCB.LNKA, 0 }, + // AC97 0:1e.2, 0:1e.3 + Package() { 0x001effff, 0, _SB.PCI0.LPCB.LNKG, 0 }, + Package() { 0x001effff, 1, _SB.PCI0.LPCB.LNKE, 0 }, + // LPC device 0:1f.0 + Package() { 0x001fffff, 0, _SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001fffff, 1, _SB.PCI0.LPCB.LNKD, 0 }, + Package() { 0x001fffff, 3, _SB.PCI0.LPCB.LNKA, 0 } + }) + } +} diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 1715c47..67b8085 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -916,8 +916,34 @@ static void i945_prepare_resume(int s3resume) } }
+static void i945_setup_interrupts(void) +{ + /* Device 1f interrupt pin register */ + RCBA32(0x3100) = 0x00042220; + RCBA32(0x3108) = 0x10004321; + /* Device 1d interrupt pin register */ + RCBA32(0x310c) = 0x00214321; + /* HD Audio Interrupt */ + RCBA32(0x3110) = 0x00000001; + + /* dev irq route register */ + RCBA16(0x3140) = 0x0232; + RCBA16(0x3142) = 0x3246; + RCBA16(0x3144) = 0x0237; + RCBA16(0x3146) = 0x3201; + RCBA16(0x3148) = 0x3216; + + /* Enable IOAPIC */ + RCBA8(0x31ff) = 0x03; + + /* Enable upper 128bytes of CMOS */ + RCBA32(0x3400) = (1 << 2); +} + void i945_late_initialization(int s3resume) { + i945_setup_interrupts(); + i945_setup_egress_port();
ich7_setup_root_complex_topology(); diff --git a/src/southbridge/intel/i82801gx/chip.h b/src/southbridge/intel/i82801gx/chip.h index 76fc90e..c61ec98 100644 --- a/src/southbridge/intel/i82801gx/chip.h +++ b/src/southbridge/intel/i82801gx/chip.h @@ -21,18 +21,6 @@ #define SOUTHBRIDGE_INTEL_I82801GX_CHIP_H
struct southbridge_intel_i82801gx_config { - /** - * Interrupt Routing configuration - * If bit7 is 1, the interrupt is disabled. - */ - uint8_t pirqa_routing; - uint8_t pirqb_routing; - uint8_t pirqc_routing; - uint8_t pirqd_routing; - uint8_t pirqe_routing; - uint8_t pirqf_routing; - uint8_t pirqg_routing; - uint8_t pirqh_routing;
/** * GPI Routing configuration diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 80abb78..71f0fb5 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -95,16 +95,20 @@ static void i82801gx_pirq_init(device_t dev) device_t irq_dev; /* Get the chip configuration */ config_t *config = dev->chip_info; + const u8 pirq_routing[] = { + 0xa, 0xa, 0xa, 0xa, + 0xb, 0xb, 0xa, 0xa + };
- pci_write_config8(dev, PIRQA_ROUT, config->pirqa_routing); - pci_write_config8(dev, PIRQB_ROUT, config->pirqb_routing); - pci_write_config8(dev, PIRQC_ROUT, config->pirqc_routing); - pci_write_config8(dev, PIRQD_ROUT, config->pirqd_routing); + pci_write_config8(dev, PIRQA_ROUT, pirq_routing[0]); + pci_write_config8(dev, PIRQB_ROUT, pirq_routing[1]); + pci_write_config8(dev, PIRQC_ROUT, pirq_routing[2]); + pci_write_config8(dev, PIRQD_ROUT, pirq_routing[3]);
- pci_write_config8(dev, PIRQE_ROUT, config->pirqe_routing); - pci_write_config8(dev, PIRQF_ROUT, config->pirqf_routing); - pci_write_config8(dev, PIRQG_ROUT, config->pirqg_routing); - pci_write_config8(dev, PIRQH_ROUT, config->pirqh_routing); + pci_write_config8(dev, PIRQE_ROUT, pirq_routing[4]); + pci_write_config8(dev, PIRQF_ROUT, pirq_routing[5]); + pci_write_config8(dev, PIRQG_ROUT, pirq_routing[6]); + pci_write_config8(dev, PIRQH_ROUT, pirq_routing[7]);
/* Eric Biederman once said we should let the OS do this. * I am not so sure anymore he was right. @@ -119,10 +123,10 @@ static void i82801gx_pirq_init(device_t dev) int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN);
switch (int_pin) { - case 1: /* INTA# */ int_line = config->pirqa_routing; break; - case 2: /* INTB# */ int_line = config->pirqb_routing; break; - case 3: /* INTC# */ int_line = config->pirqc_routing; break; - case 4: /* INTD# */ int_line = config->pirqd_routing; break; + case 1: /* INTA# */ int_line = pirq_routing[0]; break; + case 2: /* INTB# */ int_line = pirq_routing[1]; break; + case 3: /* INTC# */ int_line = pirq_routing[2]; break; + case 4: /* INTD# */ int_line = pirq_routing[3]; break; }
if (!int_line)