Attention is currently required from: Angel Pons, Arthur Heymans, Saurabh Mishra, Subrata Banik.
Ashish Kumar Mishra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82079?usp=email )
Change subject: block/fast_spi: Use read32p/write32p for spi rw ......................................................................
Patch Set 2:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/82079/comment/da7d9c75_c2254825 : PS2, Line 9: The memcpy impl. for : x86_64 changed to 8 byte copy and due to 4 byte limit, spi rw fails. MRC : cache rw regression observed in existing X86_64 platforms. Hence update : rw ops to use read32p/write32p.
Maybe change this to say that the hardware only accepts at most dword transactions at most which won […]
Acknowledged
File src/soc/intel/common/block/fast_spi/fast_spi_flash.c:
https://review.coreboot.org/c/coreboot/+/82079/comment/1d36861f_ecf594c1 : PS2, Line 80: const uint8_t *byte_ptr = (const uint8_t *)data; : size_t bytes_to_copy; : union { : uint32_t full; : uint8_t bytes[4]; : } dword; : : for (size_t i = 0; i < len; i += 4) { : dword.full = 0; : : bytes_to_copy = (len - i < 4) ? len - i : 4; : for (size_t j = 0; j < bytes_to_copy; j++) : dword.bytes[j] = byte_ptr[i + j]; : : write32p(ctx->mmio_base + SPIBAR_FDATA(i >> 2), dword.full); : }
This is what I suggested in CB:81959 but back then I wasn't sure if the hardware can also accept s […]
A similar impl. I had done for memcpy replacement earlier, however I found the current patchset code easier/simpler. Anyways, I'll verify the test with these new suggestions and update the patch. Thanks.