[coreboot-gerrit] Change in coreboot[master]: mb/google/dedede: Enable LTR reporting for PCIe root port

[Aamir Bohra (Code Review)]

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43610 )

Change subject: mb/google/dedede: Enable LTR reporting for PCIe root port
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mb/google/dedede: Enable LTR reporting for PCIe root port

Signed-off-by: Aamir Bohra 
Change-Id: I45f33248904ed8f3606077bee914befca51043d0
---
M src/mainboard/google/dedede/variants/baseboard/devicetree.cb
1 file changed, 3 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/43610/1

diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
index e126129..0dabafb 100644
--- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
@@ -95,6 +95,9 @@
    register "PcieClkSrcUsage[4]" = "0xff"
    register "PcieClkSrcUsage[5]" = "0xff"

+	# PCIe RP LTR configuration
+	register "PcieRpLtrEnable[7]" = "1"
+
    # PCIE Clock Request to Clock Source Mapping
    register "PcieClkSrcClkReq[0]" = "0"
    register "PcieClkSrcClkReq[1]" = "1"