Attention is currently required from: Jérémy Compostella, Shuo Liu, yuchi.chen@intel.com.
Elyes Haouas has posted comments on this change by yuchi.chen@intel.com. ( https://review.coreboot.org/c/coreboot/+/83321?usp=email )
Change subject: src/soc/intel/snowridge: add support for Intel Atom Snow Ridge SoC ......................................................................
Patch Set 3:
(3 comments)
File src/soc/intel/snowridge/acpi/pci_irqs.asl:
https://review.coreboot.org/c/coreboot/+/83321/comment/95ed533a_bdee9108?usp... : PS2, Line 19: ShiftLeft Please use ASL2 syntax
https://review.coreboot.org/c/coreboot/+/83321/comment/96a7a620_73a39099?usp... : PS2, Line 26: Decrement (Local0) \ : Store (Local0, ^^PRC##id) Please use ASL2 syntax
https://review.coreboot.org/c/coreboot/+/83321/comment/30403c45_dd5afc45?usp... : PS2, Line 30: \ : If (And (^^PRC##id, ^^IREN)) \ : { \ : Return (0x9) \ : } \ : Else \ : { \ : Return (0xb) \ : } \ : } \ : Method (_DIS, 0, Serialized) \ : { \ : Or(^^IREN, PRC##id, PRC##id) \ : } \ : } Please use ASL2 syntax
same for all *.asl files, please check.