Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42788
to look at the new patch set (#2).
Change subject: soc/intel/tigerlake: Add SkipCpuReplacementCheck to chip options ......................................................................
soc/intel/tigerlake: Add SkipCpuReplacementCheck to chip options
Add SkipCpuReplacementCheck to chip options to control UPD FSPM SkipCpuReplacementCheck from device tree. This UPD allows to skip CPU replacement check to avoid forced MRC traning with platforms with soldered down SoC.
TEST=boot and verified with volteer
Change-Id: Ic5782723ac3a204f2af657fac9944fb41fc03f4d Signed-off-by: Jamie Ryu jamie.m.ryu@intel.com --- M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/romstage/fsp_params.c 2 files changed, 9 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/42788/2