Attention is currently required from: Dinesh Gehlot, Kapil Porwal, Nick Vaccaro, Subrata Banik.
Michał Żygowski has posted comments on this change by Michał Żygowski. ( https://review.coreboot.org/c/coreboot/+/83356?usp=email )
Change subject: soc/intel/alderlake/tcss: Add definition of IOM_READY bit ......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS1: Unfortunately I didn't find documentation of this bit in the Core and Uncore specification. I would have to dig in other documents probably.
What also would be interesting is how long it's supposed to take.
That's a good question. For this platform 2 seconds is the shortest time required to successfully poll this bit (determined with trial and error process). Intel documentation says the BIOS can start polling about 10ms atfer DRAM Init Done message is sent to ME, so ME is supposed to start fetching TCSS IP FW right after MRC. It takes surprisingly long for this platform. Typically IOM is ready when other platforms enter Silicon Init.
If it's necessary on the resume path too (just out of curiosity).
TBH, I haven't checked how does it look like on S3 resume.