Attention is currently required from: Hung-Te Lin, Kiwi Liu, Mengqi Zhang, Paul Menzel, Yidi Lin.
Hello Hung-Te Lin, Mengqi Zhang, Yidi Lin, Yu-Ping Wu, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/84298?usp=email
to look at the new patch set (#17).
Change subject: soc/mediatek/common: Correct eMMC src clk frequency to 400 MHz ......................................................................
soc/mediatek/common: Correct eMMC src clk frequency to 400 MHz
Mediatek SoCs start operating at eMMC clock around 3MHz right after power-on due to wrong src_hz value. In JEDEC spec, eMMC clock needs under 400kHz.
When we need to set a clock output frequency, we actually set a frequency division value. Originally, we set the source clock frequency to 50MHz, the target frequency to 400KHz, and get the division value 128. However, the actual source clock frequency is 400MHz, so the final actual output is 400MHz/128=3.125MHz.
So we correct source clock frequency to 400MHz for eMMC output clock of 400KHz.
BUG=b:356578805 TEST=test boot ok; measure eMMC clock ok; NOT impact boot time
Change-Id: I9c8836b23fb21e9b0bdc80fbe85142ea0fa5e381 Signed-off-by: Mengqi Zhang mengqi.zhang@mediatek.corp-partner.google.com Signed-off-by: Kiwi Liu kiwi.liu@mediatek.corp-partner.google.com --- M src/soc/mediatek/common/msdc.c 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/84298/17