Attention is currently required from: Michał Żygowski, Piotr Król, Tarun Tuli.
Yuchen He has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/76030?usp=email )
Change subject: mb/{cfl,cml,whl}: Use true/false macros for DdiPortCHpd dt option ......................................................................
mb/{cfl,cml,whl}: Use true/false macros for DdiPortCHpd dt option
The true/false macros give the reader a better understanding about how the option should be used. Thus, replace 0/1 with false/true.
While on it, remove the quotes from the option name and from the value.
Coffeelake, Cometlake and Whiskeylake mainboards which use that option were changed by the following command ran from the top level directory.
dt_line="chip soc/intel/cannonlake" && \ option="DdiPortCHpd" && \ grep -r "${dt_line}" src/mainboard | \ cut -d ':' -f 1 | \ xargs sed -i'' -e "s/"${option}".*=.*"1"/${option} = true/g" -e "s/"${option}".*=.*"0"/${option} = false/g"
Change-Id: Ib201bde58648d35623c2f36469c045dde6464b1e Signed-off-by: lilacious yuchenhe126@gmail.com --- M src/mainboard/google/drallion/variants/drallion/devicetree.cb M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M src/mainboard/google/puff/variants/baseboard/devicetree.cb M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/google/sarien/variants/sarien/devicetree.cb M src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb M src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb M src/mainboard/protectli/vault_cml/devicetree.cb 8 files changed, 8 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/76030/1
diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index b0562b3..3b01655 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -56,7 +56,7 @@ register DdiPortEdp = true # Enable HPD for DDI ports B/C register DdiPortBHpd = true - register "DdiPortCHpd" = "1" + register DdiPortCHpd = true # Enable DDC for DDI port B register "DdiPortBDdc" = "1"
diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 5054304..56926f3 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -40,7 +40,7 @@ register DdiPortEdp = true # Enable HPD for DDI ports B/C register DdiPortBHpd = true - register "DdiPortCHpd" = "1" + register DdiPortCHpd = true register "tcc_offset" = "10" # TCC of 90C # Unlock GPIO pads register "PchUnlockGpioPads" = "1" diff --git a/src/mainboard/google/puff/variants/baseboard/devicetree.cb b/src/mainboard/google/puff/variants/baseboard/devicetree.cb index 14e10dd..1240333 100644 --- a/src/mainboard/google/puff/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/puff/variants/baseboard/devicetree.cb @@ -40,7 +40,7 @@ register DdiPortEdp = true # Enable HPD for DDI ports B/C register DdiPortBHpd = true - register "DdiPortCHpd" = "1" + register DdiPortCHpd = true register "tcc_offset" = "10" # TCC of 90C # Unlock GPIO pads register "PchUnlockGpioPads" = "1" diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index 41efb92..6e47bb9 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -45,7 +45,7 @@ register DdiPortEdp = true # Enable HPD for DDI ports B/C register DdiPortBHpd = true - register "DdiPortCHpd" = "1" + register DdiPortCHpd = true # Enable DDC for DDI port B register "DdiPortBDdc" = "1"
diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index f9a9729..8d318db 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -48,7 +48,7 @@ register DdiPortEdp = true # Enable HPD for DDI ports B/C register DdiPortBHpd = true - register "DdiPortCHpd" = "1" + register DdiPortCHpd = true # Enable DDC for DDI port B register "DdiPortBDdc" = "1"
diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb index a28f8ac..30052c6 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb @@ -6,7 +6,7 @@ register DdiPortEdp = true # Enable HPD for DDI ports B/C register DdiPortBHpd = true - register "DdiPortCHpd" = "1" + register DdiPortCHpd = true register "DdiPortDHpd" = "1" register "DdiPortFHpd" = "1" # Enable DDC for DDI ports B/C diff --git a/src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb index 3b1ca28..f1d4fda 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb @@ -6,7 +6,7 @@ register DdiPortEdp = true # Enable HPD for DDI ports B/C/D/F register DdiPortBHpd = true - register "DdiPortCHpd" = "1" + register DdiPortCHpd = true register "DdiPortDHpd" = "1" register "DdiPortFHpd" = "1" # Enable DDC for DDI ports B/C/D/F diff --git a/src/mainboard/protectli/vault_cml/devicetree.cb b/src/mainboard/protectli/vault_cml/devicetree.cb index 022d4db..c21c34a 100644 --- a/src/mainboard/protectli/vault_cml/devicetree.cb +++ b/src/mainboard/protectli/vault_cml/devicetree.cb @@ -24,7 +24,7 @@
# Enable HPD for DDI ports B/C register DdiPortBHpd = true # HDMI - register "DdiPortCHpd" = "1" # USB Type-C + register DdiPortCHpd = true # USB Type-C
# Enable DDC for DDI port B register "DdiPortBDdc" = "1" # HDMI