Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/42513 )
Change subject: tigerlake: enable tcc_offset functionality ......................................................................
tigerlake: enable tcc_offset functionality
This enables Thermal Control Circuit (TCC) activation feature to set tcc_offset to new value in devicetree.
BUG=None BRANCH=None TEST=Built for volteer platform and verified the MSR value.
Change-Id: I36b0d6aad4be8a9cbb145dcd66d65235d3f6ac35 Signed-off-by: Sumeet R Pawnikar sumeet.r.pawnikar@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/42513 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org --- M src/soc/intel/tigerlake/cpu.c M src/soc/intel/tigerlake/fsp_params.c 2 files changed, 6 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved
diff --git a/src/soc/intel/tigerlake/cpu.c b/src/soc/intel/tigerlake/cpu.c index ec78d15..9a96f8f 100644 --- a/src/soc/intel/tigerlake/cpu.c +++ b/src/soc/intel/tigerlake/cpu.c @@ -216,4 +216,7 @@ { if (mp_init_with_smm(cpu_bus, &mp_ops)) printk(BIOS_ERR, "MP initialization failure.\n"); + + /* Thermal throttle activation offset */ + configure_tcc_thermal_target(); } diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index 3fbb89a..a612427 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -213,6 +213,9 @@ /* Enable TCPU for processor thermal control */ params->Device4Enable = config->Device4Enable;
+ /* Set TccActivationOffset */ + params->TccActivationOffset = config->tcc_offset; + /* LAN */ dev = pcidev_path_on_root(PCH_DEVFN_GBE); if (!dev)