[coreboot-gerrit] [S] Change in coreboot[master]: mb/intel/mtlrvp: Enable PCIE Advanced Error Reporting

[Harsha B R (Code Review)]

Harsha B R has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/72874 )

Change subject: mb/intel/mtlrvp: Enable PCIE Advanced Error Reporting
......................................................................

mb/intel/mtlrvp: Enable PCIE Advanced Error Reporting

This patch enables PCI Express Advanced Error Reporting Capability for
WWAN, WLAN, and SSD root ports. On enabling PCIE_RP_AER, PCIE device
will automatically report (if any error) about the error nature to the
corresponding PCIe root port.

BUG=b:224325352
BRANCH=None
TEST=Build and boot mtlrvp to ChromeOS.

Signed-off-by: Harsha B R 
Change-Id: Iab8619818e2219b41287b895513eb04b0464401e
---
M src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb
1 file changed, 23 insertions(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/72874/1

diff --git a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb
index ddb80026..01a02f1 100644
--- a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb
+++ b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb
@@ -99,7 +99,7 @@
    		register "pcie_rp[PCIE_RP(7)]" = "{
    			.clk_src = 1,
    			.clk_req = 1,
-				.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR,
+				.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER,
    		}"
    	end # WWAN
    	device ref pcie_rp8  on
@@ -107,7 +107,7 @@
    		register "pcie_rp[PCIE_RP(8)]" = "{
    			.clk_src = 5,
    			.clk_req = 5,
-				.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR,
+				.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER,
    		}"
    	end # WLAN
    	device ref pcie_rp10 on
@@ -115,7 +115,7 @@
    		register "pcie_rp[PCIE_RP(10)]" = "{
    			.clk_src = 8,
    			.clk_req = 8,
-				.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR,
+				.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER,
    		}"
    	end # PCIE10 SSD Gen4
    	device ref pcie_rp11 on
@@ -123,7 +123,7 @@
    		register "pcie_rp[PCIE_RP(11)]" = "{
    			.clk_src = 7,
    			.clk_req = 7,
-				.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR,
+				.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER,
    		}"
    	end # PCIE11 SSD Gen4
    	device ref xhci on end