Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31567 )
Change subject: soc/cavium/cn81xx: Enable RNG for DRAM init
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Patch Set 2:
(1 comment)
https://review.coreboot.org/#/c/31567/2/src/soc/cavium/cn81xx/sdram.c
File src/soc/cavium/cn81xx/sdram.c:
https://review.coreboot.org/#/c/31567/2/src/soc/cavium/cn81xx/sdram.c@67
PS2, Line 67: /* Read back after enable so we know it is done. */
You don't need to poll any bits here know it's ready to accept the reads below? As printk() had some […]
That's what the reference code does without further comments.
Cavium hardware likes to raise exceptions if do not read certain registers after writing to them.
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