Attention is currently required from: Angel Pons, Christian Walter, Johnny Lin, Morgan Jang, Patrick Rudolph, Paul Menzel, Shuo Liu, yuchi.chen@intel.com.
Hello Angel Pons, Christian Walter, Johnny Lin, Morgan Jang, Paul Menzel, Shuo Liu, build bot (Jenkins), yuchi.chen@intel.com,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/85492?usp=email
to look at the new patch set (#8).
Change subject: mb/ocp/tiogapass: Wait for BMC ......................................................................
mb/ocp/tiogapass: Wait for BMC
The mainboard code relies on IPMI communication with the BMC.
Since the x86 and BMC start booting at the same time on ACPI G3 exit and the x86 is a bit faster, wait for the BMC to signal it's done booting by pulling GPP_F4 low.
Fixes lots of error messages in coreboot about not working IPMI: [ERROR] wait_ibf timeout! [ERROR] IPMI START WRITE failed [ERROR] ipmi_kcs_send_message failed
TEST: Once GPP_F4 is low IPMI communication over the KCS is also working on ocp/tiogapass. The log contains the line: [DEBUG] BMC ready after 125560 ms
Change-Id: I925aff1ff1ffd3d7388835e62aad2ba339e52472 Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com --- M src/mainboard/ocp/tiogapass/include/tp_pch_gpio.h M src/mainboard/ocp/tiogapass/romstage.c 2 files changed, 29 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/85492/8