[coreboot-gerrit] [XS] Change in coreboot[main]: soc/intel/alderlake: Configure DDR5 Physical channel width to 64

[Subrata Banik (Code Review)]

Attention is currently required from: Arthur Heymans, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Tarun.

Subrata Banik has posted comments on this change by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/84085?usp=email )

Change subject: soc/intel/alderlake: Configure DDR5 Physical channel width to 64
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Patch Set 1: Code-Review+2