Andrey Petrov has uploaded this change for review. ( https://review.coreboot.org/20064
Change subject: soc/intel/block/cse: Add Cannonlake SoC for HECI1 device ......................................................................
soc/intel/block/cse: Add Cannonlake SoC for HECI1 device
Instead of relying on SoC to provide a PCI device ID, add them explicitly.
Change-Id: Ida822d704b04cc4d1dfffb58003fc308bcb502d0 Signed-off-by: Andrey Petrov andrey.petrov@intel.com --- M src/soc/intel/common/block/cse/Makefile.inc M src/soc/intel/common/block/cse/cse.c 2 files changed, 7 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/20064/1
diff --git a/src/soc/intel/common/block/cse/Makefile.inc b/src/soc/intel/common/block/cse/Makefile.inc index fe7b13c..376f00f 100644 --- a/src/soc/intel/common/block/cse/Makefile.inc +++ b/src/soc/intel/common/block/cse/Makefile.inc @@ -1,2 +1,3 @@ +bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE) += cse.c romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE) += cse.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE) += cse.c diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index 7ae9b53..8b9473c 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -465,11 +465,16 @@ .init = pci_dev_init, };
+static const unsigned short pci_device_ids[] = { + 0x5a9a, /* Apollolake HECI1 device */ + 0x9de0 /* Cannonlake HEC11 device */ +}; + static const struct pci_driver cse_driver __pci_driver = { .ops = &cse_ops, .vendor = PCI_VENDOR_ID_INTEL, /* SoC/chipset needs to provide PCI device ID */ - .device = PCI_DEVICE_ID_INTEL_APL_CSE0, + .devices = pci_device_ids };
#endif