[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Disable CPU PCIe in FSP

[Shaunak Saha (Code Review)]

Hello build bot (Jenkins), Furquan Shaikh, Wonkyu Kim, Ravishankar Sarawadi, Duncan Laurie, Nick Vaccaro, Angel Pons, Tim Wawrzynczak, Patrick Rudolph, Caveh Jalali, Srinidhi N Kaushik, Raj Astekar,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/42557

to look at the new patch set (#6).

Change subject: soc/intel/tigerlake: Disable CPU PCIe in FSP
......................................................................

soc/intel/tigerlake: Disable CPU PCIe in FSP

In TGL SoC we have PCH and CPU side PCIe support. This patch
skips CPU side PCIe enablement in FSP if device is disabled in
devicetree. Disabling the initialization of CPU PCIe saves ~30ms
in FspSiliconInit!

BUG=b:158573805
BRANCH=None
TEST=Build and boot volteer and TGL RVP. Using cbmem tool measure the
boot time. FspSilicontInit time is reduced by ~30ms with this patch.

Signed-off-by: Shaunak Saha 
Change-Id: I7e8512d22b1463bc4207f80b16dcfb5d00ef4b46
---
M src/soc/intel/tigerlake/include/soc/pci_devs.h
M src/soc/intel/tigerlake/romstage/fsp_params.c
2 files changed, 7 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/42557/6