Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42440 )
Change subject: soc/intel/cannonlake: Add PchPmPwrCycDur to chip options
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Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42440/3/src/soc/intel/cannonlake/fs...
File src/soc/intel/cannonlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/42440/3/src/soc/intel/cannonlake/fs...
PS3, Line 415: PchPmPwrCycDur
As designated Pin signal assertion width values are static, so I prefer add a note for PchPmPwrCycDu […]
I think its safer to have a sanity check since it is clearly in violation of the EDS if the PwrCycDur is less than any of the assert times. It can potentially lead to difficult-to-debug problems.
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