[coreboot-gerrit] Change in coreboot[master]: soc/intel/alderlake/Kconfig: Set correct P2SB BAR for ADL PCH-S

[Michał Żygowski (Code Review)]

Attention is currently required from: Tim Wawrzynczak.
Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63460 )

Change subject: soc/intel/alderlake/Kconfig: Set correct P2SB BAR for ADL PCH-S
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soc/intel/alderlake/Kconfig: Set correct P2SB BAR for ADL PCH-S

According to Intel DOC #6030603 P2SB BAR must be at 0xe0000000 for
PCH-S.

Signed-off-by: Michał Żygowski 
Change-Id: Ie6db3f7108ff1edf62c94876412adfc6421034d8
---
M src/soc/intel/alderlake/Kconfig
1 file changed, 1 insertion(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/63460/1

diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index 27a8fb3..c534b08 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -254,6 +254,7 @@

config PCR_BASE_ADDRESS
    hex
+	default 0xe0000000 if SOC_INTEL_ALDERLAKE_PCH_S
    default 0xfd000000
    help
      This option allows you to select MMIO Base Address of sideband bus.