Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/22771
Change subject: soc/intel/cannonlake: Clean up UART code ......................................................................
soc/intel/cannonlake: Clean up UART code
Clean up and move UART related code under a single uart.c file.
Change-Id: I7eea910e065242689e87adac41281131674b39af Signed-off-by: Aamir Bohra aamir.bohra@intel.com --- M src/soc/intel/cannonlake/Makefile.inc M src/soc/intel/cannonlake/uart.c D src/soc/intel/cannonlake/uart_pch.c 3 files changed, 47 insertions(+), 68 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/22771/1
diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc index 076e76b..61318a4 100644 --- a/src/soc/intel/cannonlake/Makefile.inc +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -47,7 +47,6 @@ ramstage-y += spi.c ramstage-y += systemagent.c ramstage-$(CONFIG_UART_DEBUG) += uart.c -ramstage-$(CONFIG_UART_DEBUG) += uart_pch.c ramstage-y += vr_config.c ramstage-y += sd.c
@@ -55,7 +54,6 @@ smm-y += pmutil.c smm-y += smihandler.c smm-$(CONFIG_UART_DEBUG) += uart.c -smm-$(CONFIG_UART_DEBUG) += uart_pch.c
postcar-y += memmap.c postcar-y += pmutil.c diff --git a/src/soc/intel/cannonlake/uart.c b/src/soc/intel/cannonlake/uart.c index 66883ec..21b6417 100644 --- a/src/soc/intel/cannonlake/uart.c +++ b/src/soc/intel/cannonlake/uart.c @@ -16,16 +16,19 @@ #define __SIMPLE_DEVICE__
#include <assert.h> +#include <cbmem.h> #include <console/uart.h> +#include <device/pci.h> #include <device/pci_def.h> #include <intelblocks/gpio.h> #include <intelblocks/lpss.h> #include <intelblocks/pcr.h> #include <intelblocks/uart.h> +#include <soc/iomap.h> +#include <soc/nvs.h> #include <soc/pch.h> #include <soc/pci_devs.h> #include <soc/pcr_ids.h> -#include <soc/iomap.h>
/* Serial IO UART controller legacy mode */ #define PCR_SERIAL_IO_GPPRVRW7 0x618 @@ -48,6 +51,14 @@ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1)} /* TX */ } }; + +#if IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM) +uintptr_t uart_platform_base(int idx) +{ + /* We can only have one serial console at a time */ + return UART_BASE_0_ADDR(idx); +} +#endif
void pch_uart_init(void) { @@ -75,10 +86,40 @@ gpio_configure_pads(p->pads, ARRAY_SIZE(p->pads)); }
-#if IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM) -uintptr_t uart_platform_base(int idx) +device_t pch_uart_get_debug_controller(void) { - /* We can only have one serial console at a time */ - return UART_BASE_0_ADDR(idx); + switch (CONFIG_UART_FOR_CONSOLE) { + case 0: + return PCH_DEV_UART0; + case 1: + return PCH_DEV_UART1; + case 2: + default: + return PCH_DEV_UART2; + } } -#endif + +void pch_uart_read_resources(struct device *dev) +{ + pci_dev_read_resources(dev); + + /* Set the configured UART base address for the debug port */ + if (IS_ENABLED(CONFIG_UART_DEBUG) && uart_is_debug_controller(dev)) { + struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0); + /* Need to set the base and size for the resource allocator. */ + res->base = UART_BASE_0_ADDR(CONFIG_UART_FOR_CONSOLE); + res->size = UART_DEBUG_BASE_0_SIZE; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | + IORESOURCE_FIXED; + } +} + +bool pch_uart_init_debug_controller_on_resume(void) +{ + global_nvs_t *gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); + + if (gnvs) + return !!gnvs->uior; + + return false; +} diff --git a/src/soc/intel/cannonlake/uart_pch.c b/src/soc/intel/cannonlake/uart_pch.c deleted file mode 100644 index 42c7a04..0000000 --- a/src/soc/intel/cannonlake/uart_pch.c +++ /dev/null @@ -1,60 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Google Inc. - * Copyright (C) 2017 Intel Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <cbmem.h> -#include <device/pci.h> -#include <intelblocks/uart.h> -#include <soc/iomap.h> -#include <soc/nvs.h> -#include <soc/pci_devs.h> - -void pch_uart_read_resources(struct device *dev) -{ - pci_dev_read_resources(dev); - - /* Set the configured UART base address for the debug port */ - if (IS_ENABLED(CONFIG_UART_DEBUG) && uart_is_debug_controller(dev)) { - struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0); - /* Need to set the base and size for the resource allocator. */ - res->base = UART_BASE_0_ADDR(CONFIG_UART_FOR_CONSOLE); - res->size = UART_DEBUG_BASE_0_SIZE; - res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | - IORESOURCE_FIXED; - } -} - -bool pch_uart_init_debug_controller_on_resume(void) -{ - global_nvs_t *gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); - - if (gnvs) - return !!gnvs->uior; - - return false; -} - -device_t pch_uart_get_debug_controller(void) -{ - switch (CONFIG_UART_FOR_CONSOLE) { - case 0: - return PCH_DEV_UART0; - case 1: - return PCH_DEV_UART1; - case 2: - default: - return PCH_DEV_UART2; - } -}