[coreboot-gerrit] [XS] Change in coreboot[main]: soc/intel/common/block: Include register offsets for POWER_CTL

[Saurabh Mishra (Code Review)]

Attention is currently required from: Saurabh Mishra.

Hello Subrata Banik, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/84178?usp=email

to look at the new patch set (#3).

Change subject: soc/intel/common/block: Include register offsets for POWER_CTL
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soc/intel/common/block: Include register offsets for POWER_CTL

Details:
- Add (POWER_CTL) – Offset 0x1fc required bits.

Change-Id: Ief7f514c5837cb2f7c3158b67c4f6fed86796e71
Signed-off-by: Saurabh Mishra 
---
M src/soc/intel/common/block/include/intelblocks/msr.h
1 file changed, 3 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/84178/3