Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger, Felix Held.
Martin L Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68994 )
Change subject: soc/amd: Specify memory types supported by each chip ......................................................................
soc/amd: Specify memory types supported by each chip
This change disables support for memory types not used by each of the chips. This will in turn remove the files for those memory types from the platform builds.
Signed-off-by: Martin Roth gaumless@gmail.com Change-Id: I8c7f47b43d8d4a89630fbd645a725e61d74bc2a5 --- M src/soc/amd/cezanne/Kconfig M src/soc/amd/glinda/Kconfig M src/soc/amd/mendocino/Kconfig M src/soc/amd/morgana/Kconfig M src/soc/amd/picasso/Kconfig M src/soc/amd/stoneyridge/Kconfig 6 files changed, 44 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/68994/1
diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 11f8076..1630df2 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -28,6 +28,9 @@ select HAVE_FSP_GOP select HAVE_SMI_HANDLER select IDT_IN_EVERY_STAGE + select NO_DDR5 + select NO_DDR3 + select NO_DDR2 select PARALLEL_MP_AP_WORK select PLATFORM_USES_FSP2_0 select PROVIDES_ROM_SHARING @@ -76,6 +79,8 @@ select SOC_AMD_COMMON_FSP_PCI select SSE2 select UDK_2017_BINDING + select USE_DDR4 + select USE_LPDDR4 select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE diff --git a/src/soc/amd/glinda/Kconfig b/src/soc/amd/glinda/Kconfig index c11ece9..9e99099 100644 --- a/src/soc/amd/glinda/Kconfig +++ b/src/soc/amd/glinda/Kconfig @@ -31,6 +31,10 @@ select HAVE_FSP_GOP select HAVE_SMI_HANDLER select IDT_IN_EVERY_STAGE + select NO_DDR4 + select NO_DDR3 + select NO_DDR2 + select NO_LPDDR4 select PARALLEL_MP_AP_WORK select PLATFORM_USES_FSP2_0 select PROVIDES_ROM_SHARING @@ -81,6 +85,7 @@ select SOC_AMD_COMMON_FSP_PCI # TODO: Check if this is still correct select SSE2 select UDK_2017_BINDING + select USE_DDR5 select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE diff --git a/src/soc/amd/mendocino/Kconfig b/src/soc/amd/mendocino/Kconfig index c03dbe2..3a1a296 100644 --- a/src/soc/amd/mendocino/Kconfig +++ b/src/soc/amd/mendocino/Kconfig @@ -41,6 +41,10 @@ select HAVE_FSP_GOP select HAVE_SMI_HANDLER select IDT_IN_EVERY_STAGE + select NO_DDR4 + select NO_DDR3 + select NO_DDR2 + select NO_LPDDR4 select PARALLEL_MP_AP_WORK select PLATFORM_USES_FSP2_0 select PROVIDES_ROM_SHARING @@ -93,6 +97,7 @@ select SOC_AMD_COMMON_FSP_PCI # TODO: Check if this is still correct select SSE2 select UDK_2017_BINDING + select USE_DDR5 select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE diff --git a/src/soc/amd/morgana/Kconfig b/src/soc/amd/morgana/Kconfig index a1261c9..814cb55 100644 --- a/src/soc/amd/morgana/Kconfig +++ b/src/soc/amd/morgana/Kconfig @@ -31,6 +31,10 @@ select HAVE_FSP_GOP select HAVE_SMI_HANDLER select IDT_IN_EVERY_STAGE + select NO_DDR4 + select NO_DDR3 + select NO_DDR2 + select NO_LPDDR4 select PARALLEL_MP_AP_WORK select PLATFORM_USES_FSP2_0 select PROVIDES_ROM_SHARING @@ -81,6 +85,7 @@ select SOC_AMD_COMMON_FSP_PCI # TODO: Check if this is still correct select SSE2 select UDK_2017_BINDING + select USE_DDR5 select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index f3b982d..e852826 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -27,6 +27,10 @@ select HAVE_EM100_SUPPORT select HAVE_SMI_HANDLER select IDT_IN_EVERY_STAGE + select NO_DDR5 + select NO_DDR3 + select NO_DDR2 + select NO_LPDDR4 select PARALLEL_MP_AP_WORK select PLATFORM_USES_FSP2_0 select PROVIDES_ROM_SHARING @@ -69,6 +73,7 @@ select SOC_AMD_COMMON_FSP_DMI_TABLES select SSE2 select UDK_2017_BINDING + select USE_DDR4 select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index 53b986e..01800c1 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -18,6 +18,10 @@ select HAVE_CF9_RESET select HAVE_SMI_HANDLER select HAVE_USBDEBUG_OPTIONS + select NO_DDR5 + select NO_DDR3 + select NO_DDR2 + select NO_LPDDR4 select PARALLEL_MP_AP_WORK select RTC select SOC_AMD_PI @@ -45,6 +49,7 @@ select SOC_AMD_COMMON_BLOCK_UART select SSE2 select TSC_SYNC_LFENCE + select USE_DDR4 select X86_AMD_FIXED_MTRRS
config AMD_APU_STONEYRIDGE