Attention is currently required from: Andrey Pronin, Kangheui Won, Julius Werner, Rob Barnes, Karthik Ramasubramanian. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58870 )
Change subject: soc/amd/psp_verstage: Init TPM on S0i3 resume ......................................................................
Patch Set 9:
(3 comments)
File src/soc/amd/common/psp_verstage/psp_verstage.c:
https://review.coreboot.org/c/coreboot/+/58870/comment/6b010491_8dde32af PS9, Line 224: rv = verstage_soc_early_init(); : if (rv) { : printk(BIOS_DEBUG, "verstage_soc_early_init failed rv:%d\n", rv); : return POSTCODE_INIT_TPM_FAILED; : } Maybe we fork too early in Main. I think we can keep doing verstage_soc_early_init in Main so we have a common error path.
https://review.coreboot.org/c/coreboot/+/58870/comment/b9413adb_b9f0dda5 PS9, Line 230: verstage_mainboard_espi_init(); : /* verstage_soc_init should init i2c and eSPI */ : verstage_soc_init(); : /* : * verstage_mainboard_tpm_init may check board_id which depends on eSPI, : * so it must come after verstage_mainboard_espi_init and verstage_soc_init. : */ : verstage_mainboard_tpm_init(); Can we just make this the default flow?
We can remove the TPM and eSPI pin configs out of the early_gpio_table. This way we only have 1 way of doing things.
I think we could move all this into `verstage_mainboard_early_init` Even the `svc_get_boot_mode` call.
https://review.coreboot.org/c/coreboot/+/58870/comment/73acd090_8e6175b8 PS9, Line 280: nit: space