Elyes Haouas has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84152?usp=email )
Change subject: tree: Drop unnecessary "true/false" comments ......................................................................
tree: Drop unnecessary "true/false" comments
Change-Id: I5cd04972936c14d92295915fad65c7a45a8108d9 Signed-off-by: Elyes Haouas ehaouas@noos.fr Reviewed-on: https://review.coreboot.org/c/coreboot/+/84152 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Jakub Czapiga czapiga@google.com Reviewed-by: Angel Pons th3fanbus@gmail.com --- M src/security/vboot/misc.h M src/soc/intel/alderlake/chip.h M src/soc/intel/cannonlake/chip.h M src/soc/intel/common/block/include/intelblocks/uart.h M src/soc/intel/elkhartlake/chip.h M src/soc/intel/jasperlake/chip.h M src/soc/intel/meteorlake/chip.h M src/soc/intel/tigerlake/chip.h 8 files changed, 6 insertions(+), 65 deletions(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved Jakub Czapiga: Looks good to me, approved
diff --git a/src/security/vboot/misc.h b/src/security/vboot/misc.h index a7069f3..1b66186 100644 --- a/src/security/vboot/misc.h +++ b/src/security/vboot/misc.h @@ -22,9 +22,6 @@
/* * Check if given flag is set in the flags field in GBB header. - * Return value: - * true: Flag is set. - * false: Flag is not set. */ static inline bool vboot_is_gbb_flag_set(enum vb2_gbb_flag flag) { diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index ec6c0f5..c8005de 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -466,11 +466,7 @@ } igd_dvmt50_pre_alloc;
bool skip_ext_gfx_scan; - - /* Enable/Disable EIST. true:Enabled, false:Disabled */ bool eist_enable; - - /* Enable C6 DRAM */ bool enable_c6dram;
/* diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 97657e2..9459b88 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -237,10 +237,7 @@ /* Enables support for Teton Glacier hybrid storage device */ bool TetonGlacierMode;
- /* Enable/Disable EIST. true:Enabled, false:Disabled */ bool eist_enable; - - /* Enable C6 DRAM */ bool enable_c6dram;
/* diff --git a/src/soc/intel/common/block/include/intelblocks/uart.h b/src/soc/intel/common/block/include/intelblocks/uart.h index f140fc8..dc27d51 100644 --- a/src/soc/intel/common/block/include/intelblocks/uart.h +++ b/src/soc/intel/common/block/include/intelblocks/uart.h @@ -14,21 +14,10 @@ * 3. SOC will allow common code to set UART into legacy mode if supported. */
-/* - * Check if UART debug controller is initialized - * Returns: - * true = If debug controller PCI config space is initialized and device is - * out of reset - * false = otherwise - */ bool uart_is_controller_initialized(void);
/* * Check if dev corresponds to UART debug port controller. - * - * Returns: - * true: UART dev is debug port - * false: otherwise */ bool uart_is_debug_controller(struct device *dev);
diff --git a/src/soc/intel/elkhartlake/chip.h b/src/soc/intel/elkhartlake/chip.h index d446ef0..e3a23b2 100644 --- a/src/soc/intel/elkhartlake/chip.h +++ b/src/soc/intel/elkhartlake/chip.h @@ -258,7 +258,6 @@ uint8_t Heci2Enable; uint8_t Heci3Enable;
- /* Enable/Disable EIST. true:Enabled, false:Disabled */ bool eist_enable;
/* diff --git a/src/soc/intel/jasperlake/chip.h b/src/soc/intel/jasperlake/chip.h index 542ccb6..53bf34f 100644 --- a/src/soc/intel/jasperlake/chip.h +++ b/src/soc/intel/jasperlake/chip.h @@ -108,11 +108,7 @@ SaGv_Enabled, } SaGv;
- /* Rank Margin Tool - * - * true: Enable - * false: Disable - */ + /* Rank Margin Tool */ bool RMT;
/* USB related */ @@ -178,7 +174,6 @@ /* Gfx related */ bool SkipExtGfxScan;
- /* Enable/Disable EIST. true:Enabled, false:Disabled */ bool eist_enable;
/* Enable C6 DRAM */ @@ -263,10 +258,8 @@ uint8_t DdiPortAConfig; uint8_t DdiPortBConfig;
- /* HDP config - * - * true: Enable HDB - * false: Disable HDP + /* + * HDP config */ bool DdiPortAHpd; bool DdiPortBHpd; @@ -276,10 +269,8 @@ bool DdiPort3Hpd; bool DdiPort4Hpd;
- /* DDC config - * - * true: Enable DDC - * false: Disable DDC + /* + * DDC config */ bool DdiPortADdc; bool DdiPortBDdc; @@ -411,9 +402,6 @@
/* * Enable or Disable Acoustic Noise Mitigation feature. - * - * false: Disabled - * true: Enabled */ bool AcousticNoiseMitigation;
diff --git a/src/soc/intel/meteorlake/chip.h b/src/soc/intel/meteorlake/chip.h index e76f169..bf7bd36 100644 --- a/src/soc/intel/meteorlake/chip.h +++ b/src/soc/intel/meteorlake/chip.h @@ -209,7 +209,7 @@ SAGV_POINTS_0_1_2_3 = 0x0f, } sagv_wp_bitmap;
- /* Rank Margin Tool. true:Enable, false:Disable */ + /* Rank Margin Tool. */ bool rmt;
/* USB related */ @@ -297,8 +297,6 @@ } igd_dvmt50_pre_alloc;
bool skip_ext_gfx_scan; - - /* Enable/Disable EIST. true:Enabled, false:Disabled */ bool eist_enable;
/* diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index 6785eba..6f0adcc 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -285,8 +285,6 @@
/* Gfx related */ uint8_t SkipExtGfxScan; - - /* Enable/Disable EIST. true:Enabled, false:Disabled */ bool eist_enable;
/* Enable C6 DRAM */ @@ -504,29 +502,8 @@ * - PM_CFG.SLP_LAN_MIN_ASST_WDTH */ uint8_t PchPmPwrCycDur; - - /* - * External Clock Gate - * true = Mainboard design uses external clock gating - * false = Mainboard design does not use external clock gating - * - */ bool external_clk_gated; - - /* - * External PHY Gate - * true = Mainboard design uses external phy gating - * false = Mainboard design does not use external phy gating - * - */ bool external_phy_gated; - - /* - * External Bypass Enable - * true = Mainboard design uses external bypass rail - * false = Mainboard design does not use external bypass rail - * - */ bool external_bypass;
/* i915 struct for GMA backlight control */