[coreboot-gerrit] [S] Change in coreboot[master]: mb/google/myst: Update PCIe romstage gpios

[Karthik Ramasubramanian (Code Review)]

Attention is currently required from: Eric Lai, Jon Murphy, Martin Roth, Tim Van Patten.

Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75699?usp=email )

Change subject: mb/google/myst: Update PCIe romstage gpios
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Patch Set 2:

(1 comment)

File src/mainboard/google/myst/variants/baseboard/gpio.c:

https://review.coreboot.org/c/coreboot/+/75699/comment/35e13d07_a126b103 :
PS2, Line 207: CLK_REQ3_L
> Do we want a S5 SMI call back to assert the all the RST?

Not required. When the system enters S5, all these GPIOs automatically get reset and our boot flow gives sufficient time/delay before we reinitialize them in romstage and hit PCIe link training.