[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Configure TCSS D3Cold for pre-QS and QS platforms

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43980 )

Change subject: soc/intel/tigerlake: Configure TCSS D3Cold for pre-QS and QS platforms
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Patch Set 2:

(2 comments)

https://review.coreboot.org/c/coreboot/+/43980/2//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/43980/2//COMMIT_MSG@9 
PS2, Line 9: limitation
limitation*s*

https://review.coreboot.org/c/coreboot/+/43980/2/src/soc/intel/tigerlake/fsp... 
File src/soc/intel/tigerlake/fsp_params.c:

https://review.coreboot.org/c/coreboot/+/43980/2/src/soc/intel/tigerlake/fsp... 
PS2, Line 120: (cpu_id == CPUID_TIGERLAKE_A0)
Maybe encapsulate this in a function `static bool can_enable_tcss_d3cold(void)`? This would result in a cleaner statement here:

params->D3ColdEnable = can_enable_tcss_d3cold() && config->TcssD3ColdEnable;