Eric Lai has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75662?usp=email )
Change subject: mb/google/nissa/var/joxer: Configure the external V1p05/Vnn/VnnSx rails ......................................................................
mb/google/nissa/var/joxer: Configure the external V1p05/Vnn/VnnSx rails
This patch configures external V1p05/Vnn/VnnSx rails for Joxer to achieve the better power savings. * Enable the external V1p05, Vnn, VnnSx rails in S0i1, S0i2, S0i3, S3, S4, S5 , S0 states. * Set the supported voltage states. * Set the voltage for v1p05 and vnn. * Set the ICC max for v1p05 and vnn. Kit: 646929 - ADL N Platform Design Guide
BUG=b:285477026 TEST=Verified all the UPD values are updated with these configs.
Signed-off-by: Mark Hsieh mark_hsieh@wistron.corp-partner.google.com Change-Id: I78d2a885d577f6c1a89ab74c0da7b6544322c0d7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75662 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Eric Lai eric_lai@quanta.corp-partner.google.com Reviewed-by: Baieswara Reddy Sagili baieswara.reddy.sagili@intel.com Reviewed-by: Sumeet R Pawnikar sumeet.r.pawnikar@intel.com --- M src/mainboard/google/brya/variants/joxer/overridetree.cb 1 file changed, 15 insertions(+), 0 deletions(-)
Approvals: Baieswara Reddy Sagili: Looks good to me, but someone else must approve Eric Lai: Looks good to me, approved build bot (Jenkins): Verified Sumeet R Pawnikar: Looks good to me, approved
diff --git a/src/mainboard/google/brya/variants/joxer/overridetree.cb b/src/mainboard/google/brya/variants/joxer/overridetree.cb index 195e4bd..810f54f 100644 --- a/src/mainboard/google/brya/variants/joxer/overridetree.cb +++ b/src/mainboard/google/brya/variants/joxer/overridetree.cb @@ -12,6 +12,21 @@ register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for PCIe WLAN register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for CNVi WLAN
+ # Configure external V1P05/Vnn/VnnSx Rails + register "ext_fivr_settings" = "{ + .configure_ext_fivr = 1, + .v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX & ~FIVR_ENABLE_S0, + .vnn_enable_bitmap = FIVR_ENABLE_ALL_SX, + .vnn_sx_enable_bitmap = FIVR_ENABLE_ALL_SX, + .v1p05_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL, + .vnn_supported_voltage_bitmap = FIVR_VOLTAGE_MIN_ACTIVE, + .v1p05_voltage_mv = 1050, + .vnn_voltage_mv = 780, + .vnn_sx_voltage_mv = 1050, + .v1p05_icc_max_ma = 500, + .vnn_icc_max_ma = 500, + }" + # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value |