Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43741 )
Change subject: Enable long cr50 ready pulses for Tigerlake systems ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43741/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/43741/2//COMMIT_MSG@15 PS2, Line 15: to FSP. For Volteer (and future Tigerlake boards) we enable mode S0i3.4
all this passing around is only necessary because trying to initialize the Cr50 SPI before FSP-S leads to some not understood problems when trying to use it again afterwards, which doesn't sound like a very satisfactory reason. Is there no way to find and fix that problem?
+1. Let's please debug the issue we are seeing rather than working around it. From the symptoms currently, it seems like the issue is mostly because of some broken behavior within FSP. Have you dumped the GSPI registers before and after FSP has run to see the difference? Also added some more comments on the bug.