Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85811?usp=email )
Change subject: ec/google/chromeec/acpi: Add support for generic LPC memory range ......................................................................
ec/google/chromeec/acpi: Add support for generic LPC memory range
This change adds support for the generic LPC memory range configuration in the EC ACPI code.
If CONFIG_EC_GOOGLE_CHROMEEC_LPC_GENERIC_MEMORY_RANGE is enabled, the EC will use the generic LPC memory range for EMEM related communication between EC and AP Firmware. This is useful for platforms that do not have a dedicated IO range like accessed EMEM through port 62/66 or through LPC at 900h.
The generic LPC memory range is defined by the _SB.PCI0.LPCB.GLGM() method. This method returns the base address and size of the memory range.
Update the comment section to reflect the alternative source for EMEM data when CONFIG_EC_GOOGLE_CHROMEEC_LPC_GENERIC_MEMORY_RANGE is enabled.
BUG=b:354066052 TEST=Build and boot on a device with CONFIG_EC_GOOGLE_CHROMEEC_LPC_GENERIC_MEMORY_RANGE enabled.
Change-Id: I8038e2827ec7e301bad3a5a58df007f3a448bad7 Signed-off-by: Subrata Banik subratabanik@google.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/85811 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Kapil Porwal kapilporwal@google.com --- M src/ec/google/chromeec/acpi/ec.asl M src/ec/google/chromeec/acpi/emem.asl 2 files changed, 5 insertions(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Kapil Porwal: Looks good to me, approved
diff --git a/src/ec/google/chromeec/acpi/ec.asl b/src/ec/google/chromeec/acpi/ec.asl index f04ce6a..436207c 100644 --- a/src/ec/google/chromeec/acpi/ec.asl +++ b/src/ec/google/chromeec/acpi/ec.asl @@ -108,6 +108,9 @@ OperationRegion (EMEM, EmbeddedControl, EC_ACPI_MEM_MAPPED_BEGIN, EC_ACPI_MEM_MAPPED_SIZE) Field (EMEM, ByteAcc, Lock, Preserve) +#elif CONFIG(EC_GOOGLE_CHROMEEC_LPC_GENERIC_MEMORY_RANGE) + OperationRegion (EMEM, SystemMemory, _SB.PCI0.LPCB.GLGM() + 0x100, EC_MEMMAP_SIZE) + Field (EMEM, ByteAcc, NoLock, Preserve) #else OperationRegion (EMEM, SystemIO, EC_LPC_ADDR_MEMMAP, EC_MEMMAP_SIZE) Field (EMEM, ByteAcc, NoLock, Preserve) diff --git a/src/ec/google/chromeec/acpi/emem.asl b/src/ec/google/chromeec/acpi/emem.asl index 59395f3..aa63555 100644 --- a/src/ec/google/chromeec/acpi/emem.asl +++ b/src/ec/google/chromeec/acpi/emem.asl @@ -1,7 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */
/* - * EMEM data may be accessed through port 62/66 or through LPC at 900h. + * EMEM data may be accessed through port 62/66 or through LPC at 900h + * or through LPC GMR (Generic Memory Range) MMIO range. */
TIN0, 8, // Temperature 0