[coreboot-gerrit] [XS] Change in coreboot[main]: soc/mediatek/common: Reduce eMMC clock frequency to 400kHz

[Mengqi Zhang (Code Review)]

Attention is currently required from: Hung-Te Lin, Kiwi Liu, Paul Menzel, Yidi Lin.

Mengqi Zhang has posted comments on this change by Kiwi Liu. ( https://review.coreboot.org/c/coreboot/+/84298?usp=email )

Change subject: soc/mediatek/common: Reduce eMMC clock frequency to 400kHz
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Patch Set 14:

(1 comment)

File src/soc/mediatek/common/msdc.c:

https://review.coreboot.org/c/coreboot/+/84298/comment/62b41a33_c679e4bf?usp... :
PS12, Line 353: msdc_debug("sclk: %d\n", sclk);
> can you attach this log to the commit message ? (before and after the patch)

before patch:
[DEBUG]  sclk: 390625   
after patch:
[DEBUG]  sclk: 400000

I think this log is not the key point. The variable sclk represents the output frequency value calculated after the source clock frequency is divided.
You can refer to the code in lines 338 and 339 for the specific calculation method.
Let's take the before patch log as an example. hclk = 50MHz, clock = 400KHz, so div = 32, sclk = (50MHz / 4) / 32 = 390625Hz.
What ultimately changes the output clock frequency is the div. You can refer to the code in lines 347 and 348.
div = 32(before patch)
div = 250(after patch)

div related register description:
MMC/SD card clock divider
The register field controls clock frequency of serial clock on MMC/SD bus
12'h0: msdc_ck = msdc_src_ck * 1/2
others: msdc_ck = msdc_src_ck * 1/(4 * value)

So after patch, output clock frequency is 400M / (4 * 250) = 400KHz