[coreboot-gerrit] [M] Change in coreboot[master]: [WIP]src/soc/intel/alderlake: Add IBECC to Alderlake

[Maximilian Brune (Code Review)]

Maximilian Brune has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68756 )

Change subject: [WIP]src/soc/intel/alderlake: Add IBECC to Alderlake
......................................................................

[WIP]src/soc/intel/alderlake: Add IBECC to Alderlake

Signed-off-by: Maximilian Brune 
Change-Id: I9cc2ed6defa1223aa422b9b0d8145f8f8b3dd12e
---
M src/soc/intel/alderlake/chip.h
M src/soc/intel/alderlake/romstage/fsp_params.c
2 files changed, 62 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/68756/1

diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h
index 4cb6066..47a2bf7 100644
--- a/src/soc/intel/alderlake/chip.h
+++ b/src/soc/intel/alderlake/chip.h
@@ -19,6 +19,41 @@
 #include <soc/vr_config.h>
 #include <stdint.h>

+/* Define config parameters for In-Band ECC (IBECC). */
+#define MAX_IBECC_REGIONS	8
+
+/* In-Band ECC Operation Mode */
+enum ibecc_mode {
+	IBECC_MODE_PER_REGION,
+	IBECC_MODE_NONE,
+	IBECC_MODE_ALL
+};
+
+/* Error Injection Control */
+//enum ibecc_err_injection_control {
+//	IBECC_ERR_INJ_NONE,
+//	IBECC_ERR_INJ_
+//};
+
+struct ibecc_config {
+	bool enable;
+	enum ibecc_mode mode;
+	bool range_enable[MAX_IBECC_REGIONS];
+	uint16_t range_base[MAX_IBECC_REGIONS];
+	uint16_t range_mask[MAX_IBECC_REGIONS];
+	/* IBECC Error Injection Control
+  0: No Error Injection, 1:Inject Correctable Error Address match, 3:Inject Correctable
+  Error on insertion counter, 5: Inject Uncorrectable Error Address match, 7:Inject
+  Uncorrectable Error on insertion counter */
+	//uint8_t err_injection_control;
+	///* Address to match against for ECC error injection */
+	//uint64_t err_injection_address;
+	///* Mask to match against for ECC error injection */
+	//uint64_t err_injection_mask;
+	///* Number of transactions between ECC error injection */
+	//uint32_t err_injection_count;
+};
+
 /* Types of different SKUs */
 enum soc_intel_alderlake_power_limits {
    ADL_P_142_242_282_15W_CORE,
@@ -271,6 +306,9 @@
    /* TCC activation offset */
    uint32_t tcc_offset;

+	/* In-Band ECC (IBECC) configuration */
+	struct ibecc_config ibecc;
+
    /* System Agent dynamic frequency support. Only effects ULX/ULT CPUs.
     * When enabled memory will be training at two different frequencies.
     * 0:Disabled, 1:FixedPoint0, 2:FixedPoint1, 3:FixedPoint2,
diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c
index c0bdb0d..63a1d60 100644
--- a/src/soc/intel/alderlake/romstage/fsp_params.c
+++ b/src/soc/intel/alderlake/romstage/fsp_params.c
@@ -366,6 +366,20 @@

for (size_t i = 0; i < ARRAY_SIZE(fill_fspm_params); i++)
    	fill_fspm_params[i](m_cfg, config);
+
+	/* In-Band ECC configuration */
+	if (config->ibecc.enable) {
+		m_cfg->Ibecc = !!config->ibecc.enable;
+		m_cfg->IbeccOperationMode = config->ibecc.mode;
+		if (m_cfg->IbeccOperationMode == IBECC_MODE_PER_REGION) {
+			FSP_ARRAY_LOAD(m_cfg->IbeccProtectedRangeEnable,
+				       config->ibecc.range_enable);
+			FSP_ARRAY_LOAD(m_cfg->IbeccProtectedRangeBase,
+				       config->ibecc.range_base);
+			FSP_ARRAY_LOAD(m_cfg->IbeccProtectedRangeMask,
+				       config->ibecc.range_mask);
+		}
+	}
 }

void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)