[coreboot-gerrit] Change in coreboot[master]: mb/google/zork: add UPDS updating function before runing FSP

[chris wang (Code Review)]

Attention is currently required from: Chris Wang.
Hello Chris Wang,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/51181

to review the following change.

Change subject: mb/google/zork: add UPDS updating function before runing FSP
......................................................................

mb/google/zork: add UPDS updating function before runing FSP

Add the UPS updating hook in early stage for customization.

Change-Id: I38ff7c2dd1a46b16c12d43bb76835977bb264b10

BUG=b:117719313
BRANCH=zork
TEST=build,check the hook function been executed.

Signed-off-by: Chris Wang 
Change-Id: I4954a438a51b29b086015624127e651fd06f971b
---
M src/mainboard/google/zork/Makefile.inc
A src/mainboard/google/zork/romstage.c
M src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h
A src/soc/amd/picasso/include/soc/romstage.h
M src/soc/amd/picasso/romstage.c
5 files changed, 36 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/51181/1

diff --git a/src/mainboard/google/zork/Makefile.inc b/src/mainboard/google/zork/Makefile.inc
index 8a9d7af..4aac8f4 100644
--- a/src/mainboard/google/zork/Makefile.inc
+++ b/src/mainboard/google/zork/Makefile.inc
@@ -4,6 +4,7 @@

romstage-y += chromeos.c
 romstage-y += sku_id.c
+romstage-y += romstage.c

ramstage-y += chromeos.c
 ramstage-y += ec.c
diff --git a/src/mainboard/google/zork/romstage.c b/src/mainboard/google/zork/romstage.c
new file mode 100644
index 0000000..5c5603a
--- /dev/null
+++ b/src/mainboard/google/zork/romstage.c
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <baseboard/variants.h>
+#include <console/console.h>
+#include <console/uart.h>
+#include <device/device.h>
+#include <soc/pci_devs.h>
+#include <soc/romstage.h>
+#include "chip.h"
+
+void __weak variant_upds_update(void) {}
+
+void mainboard_upds_update(void)
+{
+	variant_upds_update();
+}
+
+void romstage_mainboard_init(void)
+{
+	mainboard_upds_update();
+}
diff --git a/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h
index ac600de..8ec32cc 100644
--- a/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h
+++ b/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h
@@ -32,6 +32,8 @@
  */
 const struct soc_amd_gpio *variant_sleep_gpio_table(size_t *size, int slp_typ);

+void variant_upds_update(void);
+
 /* Program any required GPIOs at the finalize phase */
 void finalize_gpios(int slp_typ);
 /* Modify devictree settings during ramstage. */
diff --git a/src/soc/amd/picasso/include/soc/romstage.h b/src/soc/amd/picasso/include/soc/romstage.h
new file mode 100644
index 0000000..9a91619
--- /dev/null
+++ b/src/soc/amd/picasso/include/soc/romstage.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_ROMSTAGE_H_
+#define _SOC_ROMSTAGE_H_
+
+void romstage_mainboard_init(void);
+void mainboard_upds_update(void);
+
+#endif /* _SOC_ROMSTAGE_H_ */
diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c
index c085a53..a2b0d49 100644
--- a/src/soc/amd/picasso/romstage.c
+++ b/src/soc/amd/picasso/romstage.c
@@ -16,10 +16,12 @@
 #include <soc/acpi.h>
 #include <soc/mrc_cache.h>
 #include <soc/pci_devs.h>
+#include <soc/romstage.h>
 #include <types.h>
 #include "chip.h"
 #include <fsp/api.h>

+void __weak romstage_mainboard_init(void) {}
 static struct chipset_power_state chipset_state;

static void fill_chipset_state(void)
@@ -152,6 +154,7 @@
    fill_chipset_state();

post_code(0x43);
+	romstage_mainboard_init();
    fsp_memory_init(acpi_is_wakeup_s3());
    soc_update_mrc_cache();