Won Chung has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59401 )
Change subject: ec/google/chromeec: Add PLD to EC conn in ACPI table ......................................................................
ec/google/chromeec: Add PLD to EC conn in ACPI table
BUG=b:202446737 TEST=emerge-brya coreboot
Signed-off-by: Won Chung wonchung@google.com Change-Id: Ibc56ecd4e8954ffaace3acd9528a064b5fa2cf6f --- M src/acpi/acpigen_usb.c M src/ec/google/chromeec/ec_acpi.c M src/include/acpi/acpigen_usb.h 3 files changed, 35 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/59401/1
diff --git a/src/acpi/acpigen_usb.c b/src/acpi/acpigen_usb.c index 7448b3b..2868fee 100644 --- a/src/acpi/acpigen_usb.c +++ b/src/acpi/acpigen_usb.c @@ -2,6 +2,7 @@
#include <acpi/acpi.h> #include <acpi/acpi_device.h> +#include <acpi/acpi_pld.h> #include <acpi/acpigen.h> #include <acpi/acpigen_usb.h>
@@ -132,5 +133,8 @@ add_custom_dsd_property(dsd, port_number); acpi_dp_write(dsd);
+ /* Add PLD */ + acpigen_write_pld(config->pld); + acpigen_pop_len(); /* Device */ } diff --git a/src/ec/google/chromeec/ec_acpi.c b/src/ec/google/chromeec/ec_acpi.c index 0598364..d1bc038 100644 --- a/src/ec/google/chromeec/ec_acpi.c +++ b/src/ec/google/chromeec/ec_acpi.c @@ -2,6 +2,7 @@
#include <acpi/acpi.h> #include <acpi/acpi_device.h> +#include <acpi/acpi_pld.h> #include <acpi/acpigen.h> #include <acpi/acpigen_ps2_keybd.h> #include <acpi/acpigen_usb.h> @@ -117,6 +118,28 @@ acpi_dp_add_string(dsd, "port-location", port_location_to_str(port_caps.port_location)); }
+static void get_pld_from_usb_ports(struct acpi_pld *pld, + struct device *usb2_port, struct device *usb3_port, + struct device *usb4_port) +{ + struct drivers_usb_acpi_config *config; + + config = NULL; + if (usb4_port) + config = usb4_port->chip_info; + else if (usb3_port) + config = usb3_port->chip_info; + else if (usb2_port) + config = usb2_port->chip_info; + + if (config) { + if (config->use_custom_pld) + *pld = config->custom_pld; + else + acpi_pld_fill_usb(pld, config->type, &config->group); + } +} + static void fill_ssdt_typec_device(const struct device *dev) { struct ec_google_chromeec_config *config = dev->chip_info; @@ -126,6 +149,7 @@ struct device *usb2_port; struct device *usb3_port; struct device *usb4_port; + struct acpi_pld pld;
if (google_chromeec_get_num_pd_ports(&num_ports)) return; @@ -146,6 +170,8 @@ usb4_port = NULL; get_usb_port_references(i, &usb2_port, &usb3_port, &usb4_port);
+ get_pld_from_usb_ports(&pld, usb2_port, usb3_port, usb4_port); + struct typec_connector_class_config typec_config = { .power_role = port_caps.power_role_cap, .try_power_role = port_caps.try_power_role_cap, @@ -156,6 +182,7 @@ .orientation_switch = config->mux_conn[i], .usb_role_switch = config->mux_conn[i], .mode_switch = config->mux_conn[i], + .pld = &pld, };
acpigen_write_typec_connector(&typec_config, i, add_port_location); diff --git a/src/include/acpi/acpigen_usb.h b/src/include/acpi/acpigen_usb.h index efc31f3..8042874 100644 --- a/src/include/acpi/acpigen_usb.h +++ b/src/include/acpi/acpigen_usb.h @@ -3,6 +3,8 @@ #ifndef ACPI_ACPIGEN_USB_H #define ACPI_ACPIGEN_USB_H
+#include <acpi/acpi_pld.h> + enum usb_typec_power_role { TYPEC_POWER_ROLE_SOURCE, TYPEC_POWER_ROLE_SINK, @@ -39,6 +41,7 @@ * host or device, for the USB port * @mode_switch: Reference to the ACPI device that controls routing of data lines to * various endpoints (xHCI, DP, etc.) on the SoC. + * @pld: Reference to PLD information. */ struct typec_connector_class_config { enum usb_typec_power_role power_role; @@ -50,6 +53,7 @@ const struct device *orientation_switch; const struct device *usb_role_switch; const struct device *mode_switch; + const struct acpi_pld *pld; };
typedef void (*add_custom_dsd_property_cb)(struct acpi_dp *dsd, int port_number);