[coreboot-gerrit] [S] Change in coreboot[main]: soc/intel/cannonlake: Hook up Intel TXT FSP UPDs

[Michał Żygowski (Code Review)]

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83727?usp=email )

Change subject: soc/intel/cannonlake: Hook up Intel TXT FSP UPDs
......................................................................

soc/intel/cannonlake: Hook up Intel TXT FSP UPDs

Set necessary parameters so that FSP can call BIOS ACM ACHECK
after MRC. It is required to perform ACHECK in certain conditions
and the Intel TXT will not function properly without calling it.

TEST=Boot Linux with tboot on Protectli VP4670 with Intel TXT enabled.

Change-Id: Ibca1c7c8a5335dab8af4888aee4c60683b72746d
Signed-off-by: Michał Żygowski 
---
M src/soc/intel/cannonlake/fsp_params.c
M src/soc/intel/cannonlake/romstage/fsp_params.c
2 files changed, 22 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/83727/1

diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c
index e1eede2..cdf8fda 100644
--- a/src/soc/intel/cannonlake/fsp_params.c
+++ b/src/soc/intel/cannonlake/fsp_params.c
@@ -687,6 +687,8 @@

params->PavpEnable = CONFIG(PAVP);

+	params->TxtEnable = CONFIG(INTEL_TXT);
+
    /*
     * Prevent FSP from programming write-once subsystem IDs by providing
     * a custom SSID table. Must have at least one entry for the FSP to
diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c
index 2b25285..860e3cb 100644
--- a/src/soc/intel/cannonlake/romstage/fsp_params.c
+++ b/src/soc/intel/cannonlake/romstage/fsp_params.c
@@ -133,6 +133,26 @@
    /* Set HECI1 PCI BAR address */
    m_cfg->Heci1BarAddress = HECI1_BASE_ADDRESS;

+/* Use pre-processor because CONFIG_INTEL_TXT_CBFS_BIOS_ACM is not defined otherwise */
+#if CONFIG(INTEL_TXT)
+	size_t acm_size = 0;
+	uintptr_t acm_base;
+
+	/* FSP will need the BIOS ACM to call ACHECK if necessary */
+	acm_base = (uintptr_t)cbfs_map(CONFIG_INTEL_TXT_CBFS_BIOS_ACM, &acm_size);
+
+	m_cfg->TxtImplemented = 1;
+	m_cfg->Txt = 1;
+	m_cfg->SinitMemorySize = CONFIG_INTEL_TXT_SINIT_SIZE;
+	m_cfg->TxtHeapMemorySize = CONFIG_INTEL_TXT_HEAP_SIZE;
+	m_cfg->TxtDprMemorySize = CONFIG_INTEL_TXT_DPR_SIZE << 20;
+	/* Set DPR base to non-zero, FSP will update it internally in MRC */
+	m_cfg->TxtDprMemoryBase = 1;
+	m_cfg->BiosAcmBase = acm_base;
+	m_cfg->BiosAcmSize = acm_size;
+	m_cfg->ApStartupBase = 1; /* Set to non-zero, FSP does NULL check */
+#endif
+
    mainboard_memory_init_params(mupd);
 }