[coreboot-gerrit] Change in coreboot[master]: soc/intel/alderlake: Trigger cse_fw_sync before DRAM Init

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55364 )

Change subject: soc/intel/alderlake: Trigger cse_fw_sync before DRAM Init
......................................................................

soc/intel/alderlake: Trigger cse_fw_sync before DRAM Init

The patch enables cse_fw_sync() before DRAM initialization.
cse_fw_sync() sends HECI commands in order to set CSE's boot partition
and to trigger CSE firmware update.
As part of CSE firmware update, coreboot sends HMRPFO_ENABLE HECI
command. Since CSE supports the command after DRAM Initialization,
cse_fw_sync() is called after DRAM initialization.

Starting from CSE Litev16.0.15.1545, CSE support HMRFPO_ENABLE command
before DRAM initialization too. So, cse_fw_sync() is called before DRAM
initialization.

BUG=b:175516533
TEST=Dependency with CSE Litev16.0.15.1545 integration

Change-Id: Iad7403650df8bc4e40aa6e48ccfeba95a5789a2d
Signed-off-by: Sridhar Siricilla 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55364
Reviewed-by: Maulik V Vaghela 
Reviewed-by: Subrata Banik 
Reviewed-by: Ronak Kanabar 
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/alderlake/romstage/romstage.c
1 file changed, 4 insertions(+), 10 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Subrata Banik: Looks good to me, approved
  Maulik V Vaghela: Looks good to me, but someone else must approve
  Ronak Kanabar: Looks good to me, but someone else must approve

diff --git a/src/soc/intel/alderlake/romstage/romstage.c b/src/soc/intel/alderlake/romstage/romstage.c
index e84eca8..d33d21f 100644
--- a/src/soc/intel/alderlake/romstage/romstage.c
+++ b/src/soc/intel/alderlake/romstage/romstage.c
@@ -129,6 +129,9 @@

s3wake = pmc_fill_power_state(ps) == ACPI_S3;

+	if (CONFIG(SOC_INTEL_CSE_LITE_SKU) && !s3wake)
+		cse_fw_sync();
+
    /*
     * Set low maximum temp threshold value used for dynamic thermal sensor
     * shutdown consideration.
@@ -140,15 +143,6 @@

fsp_memory_init(s3wake);
    pmc_set_disb();
-	if (!s3wake) {
-		/*
-		 * cse_fw_sync() must be called after DRAM initialization as
-		 * HMRFPO_ENABLE HECI command (which is used by cse_fw_sync())
-		 * is expected to be executed after DRAM initialization.
-		 */
-		if (CONFIG(SOC_INTEL_CSE_LITE_SKU))
-			cse_fw_sync();
-
+	if (!s3wake)
    	save_dimm_info();
-	}
 }