Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59501 )
Change subject: Revert "soc/amd/cezanne: Move APOB update into ramstage" ......................................................................
Revert "soc/amd/cezanne: Move APOB update into ramstage"
This reverts commit 73e0f18b35f154dc54994474448df283f51d659d.
We now support coop-threads in romstage. This means we can use the SPI DMA controller to preload the APOB while FSP-S executes.
BUG=b:179699789 TEST=Boot guybrush to OS and see APOB updating in romstage
Signed-off-by: Raul E Rangel rrangel@chromium.org Change-Id: Ibff6e53ee35e46d5b91f5ffd47faf7869375a34b --- M src/soc/amd/cezanne/romstage.c M src/soc/amd/common/block/apob/Makefile.inc M src/soc/amd/common/block/apob/apob_cache.c M src/soc/amd/common/block/include/amdblocks/apob_cache.h M src/soc/amd/picasso/romstage.c 5 files changed, 6 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/59501/1
diff --git a/src/soc/amd/cezanne/romstage.c b/src/soc/amd/cezanne/romstage.c index 4135cbc..8015c7a 100644 --- a/src/soc/amd/cezanne/romstage.c +++ b/src/soc/amd/cezanne/romstage.c @@ -2,6 +2,7 @@
#include <acpi/acpi.h> #include <amdblocks/acpimmio.h> +#include <amdblocks/apob_cache.h> #include <amdblocks/memmap.h> #include <amdblocks/pmlib.h> #include <arch/cpu.h> @@ -26,6 +27,7 @@ preload_fspm();
fsp_memory_init(acpi_is_wakeup_s3()); + soc_update_apob_cache();
/* Fixup settings FSP-M should not be changing */ fch_disable_legacy_dma_io(); diff --git a/src/soc/amd/common/block/apob/Makefile.inc b/src/soc/amd/common/block/apob/Makefile.inc index 6e217df..16baf81 100644 --- a/src/soc/amd/common/block/apob/Makefile.inc +++ b/src/soc/amd/common/block/apob/Makefile.inc @@ -1,4 +1,3 @@ ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_APOB),y) romstage-y += apob_cache.c -ramstage-y += apob_cache.c endif # CONFIG_SOC_AMD_COMMON_BLOCK_APOB diff --git a/src/soc/amd/common/block/apob/apob_cache.c b/src/soc/amd/common/block/apob/apob_cache.c index f61785d..6a0dfc8 100644 --- a/src/soc/amd/common/block/apob/apob_cache.c +++ b/src/soc/amd/common/block/apob/apob_cache.c @@ -4,7 +4,6 @@ #include <amdblocks/apob_cache.h> #include <assert.h> #include <boot_device.h> -#include <bootstate.h> #include <commonlib/helpers.h> #include <commonlib/region.h> #include <console/console.h> @@ -139,7 +138,7 @@ }
/* Save APOB buffer to flash */ -static void soc_update_apob_cache(void *unused) +void soc_update_apob_cache(void) { struct apob_base_header *apob_rom; struct region_device read_rdev, write_rdev; @@ -229,9 +228,3 @@ */ return get_apob_nv_address(); } - -/* - * BS_POST_DEVICE was chosen because this gives start_apob_cache_read plenty of time to read - * the APOB from SPI. - */ -BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, soc_update_apob_cache, NULL); diff --git a/src/soc/amd/common/block/include/amdblocks/apob_cache.h b/src/soc/amd/common/block/include/amdblocks/apob_cache.h index e91720f..6af8966 100644 --- a/src/soc/amd/common/block/include/amdblocks/apob_cache.h +++ b/src/soc/amd/common/block/include/amdblocks/apob_cache.h @@ -6,5 +6,6 @@ /* Start loading the APOB as soon as possible so it is ready by the time we need it. */ void start_apob_cache_read(void); void *soc_fill_apob_cache(void); +void soc_update_apob_cache(void);
#endif /* AMD_BLOCK_APOB_CACHE_H */ diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c index 1972410..d3ceec5 100644 --- a/src/soc/amd/picasso/romstage.c +++ b/src/soc/amd/picasso/romstage.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpi.h> +#include <amdblocks/apob_cache.h> #include <amdblocks/memmap.h> #include <amdblocks/pmlib.h> #include <arch/cpu.h> @@ -26,6 +27,7 @@
post_code(0x43); fsp_memory_init(acpi_is_wakeup_s3()); + soc_update_apob_cache();
memmap_stash_early_dram_usage();