[coreboot-gerrit] [S] Change in coreboot[main]: soc/intel/xeon_sp/spr: Enable FSP_DOES_NOT_NEED_TEMP_RAM

[Shuo Liu (Code Review)]

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Lean Sheng Tan, Patrick Rudolph, Tim Chu.

Shuo Liu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80329?usp=email )

Change subject: soc/intel/xeon_sp/spr: Enable FSP_DOES_NOT_NEED_TEMP_RAM
......................................................................

soc/intel/xeon_sp/spr: Enable FSP_DOES_NOT_NEED_TEMP_RAM

Change-Id: Ic84c4332dd5b6980ca03f6ab601b7464e0b18001
Signed-off-by: Shuo Liu 
---
M src/soc/intel/xeon_sp/spr/Kconfig
1 file changed, 2 insertions(+), 12 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/80329/1

diff --git a/src/soc/intel/xeon_sp/spr/Kconfig b/src/soc/intel/xeon_sp/spr/Kconfig
index bb88bec..fd19cff 100644
--- a/src/soc/intel/xeon_sp/spr/Kconfig
+++ b/src/soc/intel/xeon_sp/spr/Kconfig
@@ -13,6 +13,7 @@
    select SOC_INTEL_CSE_SERVER_SKU
    select XEON_SP_COMMON_BASE
    select HAVE_IOAT_DOMAINS
+	select FSP_DOES_NOT_NEED_TEMP_RAM
    help
      Intel Sapphire Rapids-SP support

@@ -64,7 +65,7 @@

config FSP_M_RC_HEAP_SIZE
    hex
-	default 0x150000
+	default 0x1B0000
    help
      On xeon_sp/spr FSP-M has two separate heap managers, one regular
      whose size and base are controllable via the StackBase and
@@ -84,17 +85,6 @@
    hex
    default 0x4000

-config FSP_TEMP_RAM_SIZE
-	hex
-	depends on FSP_USES_CB_STACK
-	default 0x60000
-	help
-	  The amount of anticipated heap usage in CAR by FSP.
-	  Refer to Platform FSP integration guide document to know
-	  the exact FSP requirement for Heap setup.  The FSP integration
-	  documentation says this needs to be at least 128KiB, but practice
-	  show this needs to be 256KiB or more.
-
 config IED_REGION_SIZE
    hex
    default 0x400000