[coreboot-gerrit] [XS] Change in coreboot[main]: src/{incl/cpu, soc/intel/cmn}: Add Extended Feature Enable Register M...

[Saurabh Mishra (Code Review)]

Attention is currently required from: Jérémy Compostella, Subrata Banik.

Saurabh Mishra has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/84174?usp=email )

Change subject: src/{incl/cpu, soc/intel/cmn}: Add Extended Feature Enable Register Macro
......................................................................

Patch Set 6:

(2 comments)

Patchset:

PS5:
> same feedback why this CL is not at main tot and inside PTL recipe ?

Moved to TOT.

File src/include/cpu/x86/msr.h:

https://review.coreboot.org/c/coreboot/+/84174/comment/0b536251_27390373?usp... :
PS4, Line 64:
> > Hi, these bits belogs to (POWER_CTL) – Offset 1fc […]

I have moved the Offset 1fc definition to src/soc/intel/common/block/include/intelblocks/msr.h.