[coreboot-gerrit] Change in coreboot[master]: soc/amd/common: fix SPI bar resource usage

[Aaron Durbin (Code Review)]

Aaron Durbin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42959 )

Change subject: soc/amd/common: fix SPI bar resource usage
......................................................................

soc/amd/common: fix SPI bar resource usage

The ACPI code was not masking off the correct bits for publishing
the SPI bar to the OS.

It resulted in a dmesg messagelike:
    system 00:00: [mem 0xfec10002-0xfec11001] has been reserved
And /proc/iomem entry
    fec10002-fec11001 : pnp 00:00

These addresses are wrong because they are including bits of a
register that are not a part of the address.

Moreover, the code does not publish the eSPI register area either.
The eSPI registers live at 0x10000 added to the SPI bar. Lastly,
both regions are less than a page so only report a page of usage
for each.

Stoney Ridge's SPI bar register defines the address as 31:6 while
Picasso's SPI bar register defines the address as 31:8. Use Picasso's
valid mask for both cases because no one is assigning addresses
that are aligned to less than 256 bytes.

With the fixes, dmesg reports:
    system 00:00: [mem 0xfec10000-0xfec10fff] has been reserved
    system 00:00: [mem 0xfec20000-0xfec20fff] has been reserved
And /proc/iomem indicates:
    fec10000-fec10fff : pnp 00:00
    fec20000-fec20fff : pnp 00:00

BUG=b:160290629

Signed-off-by: Aaron Durbin 
Change-Id: I130b5ad26d9e13b44c25fbb35a05389f9e8841ab
---
M src/soc/amd/common/acpi/lpc.asl
1 file changed, 12 insertions(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/42959/1

diff --git a/src/soc/amd/common/acpi/lpc.asl b/src/soc/amd/common/acpi/lpc.asl
index 5f290c4..e4b0689 100644
--- a/src/soc/amd/common/acpi/lpc.asl
+++ b/src/soc/amd/common/acpi/lpc.asl
@@ -26,17 +26,25 @@
    	{
    		Memory32Fixed(ReadWrite,	// Setup for fixed resource location for SPI base address
    		0x00000000,			// Address Base
-			0x00000000,			// Address Length
+			0x00001000,			// Address Length
    		BAR0				// Descriptor Name
    		)
+
+			Memory32Fixed(ReadWrite,	// Setup for fixed resource location for eSPI base address
+			0x00000000,			// Address Base
+			0x00001000,			// Address Length
+			BAR1				// Descriptor Name
+			)
    	})

Method(_CRS,0,Serialized)
    	{
    		CreateDwordField(^CRS,^BAR0._BAS,SPIB)	// Field to hold SPI base address
-			CreateDwordField(^CRS,^BAR0._LEN,SPIL)	// Field to hold SPI address length
-			Store(BAR,SPIB)		// SPI base address mapped
-			Store(0x1000,SPIL)	// 4k space mapped
+			CreateDwordField(^CRS,^BAR1._BAS,ESPB)	// Field to hold eSPI base address
+			And(BAR, 0xffffff00, Local0)
+			Store(Local0, SPIB)	// SPI base address mapped
+			Add(Local0, 0x10000, Local1)
+			Store(Local1, ESPB)	// eSPI base address mapped
    		Return(CRS)
    	}
    }