[coreboot-gerrit] [XS] Change in coreboot[main]: mb/google/nissa/var/sundance: Adjust GPIO GPP_C1 to no_pull-up

[Roger Wang (Code Review)]

Roger Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83904?usp=email )

Change subject: mb/google/nissa/var/sundance: Adjust GPIO GPP_C1 to no_pull-up
......................................................................

mb/google/nissa/var/sundance: Adjust GPIO GPP_C1 to no_pull-up

Due to internal pull-up resistor of 65Kohm in /RST pin in GT7986U(Touch Controller, we will change GPP_C1 from PP&internal pull-up to OD&no pull-up in PCH GPIO Table.

BUG=b:358472598
TEST=Build and verified test result by EE team

Change-Id: I84d1b42a39bebbcd610cebc46f979018fc79238f
Signed-off-by: Roger Wang 
---
M src/mainboard/google/brya/variants/sundance/gpio.c
1 file changed, 2 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/83904/1

diff --git a/src/mainboard/google/brya/variants/sundance/gpio.c b/src/mainboard/google/brya/variants/sundance/gpio.c
index bd36f05..711f314 100644
--- a/src/mainboard/google/brya/variants/sundance/gpio.c
+++ b/src/mainboard/google/brya/variants/sundance/gpio.c
@@ -17,7 +17,7 @@
    /* B6  : NC */
    PAD_NC_LOCK(GPP_B6, NONE, LOCK_CONFIG),
    /* C1  : SMBDATA ==> USI_RST_L */
-	PAD_CFG_TERM_GPO(GPP_C1, 1, UP_20K, DEEP),
+	PAD_CFG_GPO(GPP_C1, 1, DEEP),
    /* D3  : WCAM_RST_L ==> NC */
    PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG),
    /* D6  : SRCCLKREQ1# ==> WWAN_EN */
@@ -86,7 +86,7 @@
    /* C0  : SMBCLK ==> EN_PP3300_TCHSCR */
    PAD_CFG_GPO(GPP_C0, 1, DEEP),
    /* C1  : SMBDATA ==> USI_RST_L */
-	PAD_CFG_TERM_GPO(GPP_C1, 0, UP_20K, DEEP),
+	PAD_CFG_GPO(GPP_C1, 1, DEEP),
 };

const struct pad_config *variant_gpio_override_table(size_t *num)