[coreboot-gerrit] [XS] Change in coreboot[master]: soc/intel/xeon_sp/spr: Fix memory max capacity per processor

[Ziang Wang (Code Review)]

Attention is currently required from: Arthur Heymans, Christian Walter, Eric Lai, Felix Singer, Nico Huber, Patrick Rudolph, Paul Menzel, Tim Chu.

Ziang Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75740?usp=email )

Change subject: soc/intel/xeon_sp/spr: Fix memory max capacity per processor
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Patch Set 5:

(4 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/75740/comment/8a026e8c_378c9e80 :
PS1, Line 2: wanghao11
> Please use your full name and not the user name: […]

Done

https://review.coreboot.org/c/coreboot/+/75740/comment/1514fa78_1866ca6c :
PS1, Line 10:
> Was there a user visible problem? If yes, please describe it, and also document how you tested your  […]

Done

https://review.coreboot.org/c/coreboot/+/75740/comment/5a8ee974_91e6512c :
PS1, Line 12: Signed-off-by: wanghao11
> Ditto.

Done

File src/soc/intel/xeon_sp/spr/romstage.c:

https://review.coreboot.org/c/coreboot/+/75740/comment/065ba73b_ba545e42 :
PS1, Line 277: 	 * Persistent Memory 300 Series mapped as memory) per Socket
> Can use this way to do it? https://source.chromium. […]

@Nico: '3DS' here refers to '3D stacking‘ which is a memory packaging technology I guess, it increases the memory density. And yes, 6TiB is the sum of max. DRAM and max. Optane Mem possible.

@Eric: I agree it is a more organized way, but this change is only for SPR-SP (under xeon-sp/spr), and seems like there is only one possible case, so I am not very motivated to add a soc overrider for it...