Caesar Wang has posted comments on this change. ( https://review.coreboot.org/19557 )
Change subject: rockchip/rk3399: enable DPLL SSC for DDR EMI test on bob
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Patch Set 10:
(1 comment)
https://review.coreboot.org/#/c/19557/9/src/soc/rockchip/rk3399/clock.c
File src/soc/rockchip/rk3399/clock.c:
Line 424: u32 postdiv1, postdiv2 = 1;
Now you're already setting spreadamp to 8 above, you can get rid of this.
Done.
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