Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32095
Change subject: soc/intel/icelake: Fix chipset_power_state structure ......................................................................
soc/intel/icelake: Fix chipset_power_state structure
This patch port CL:30717 changes from CNL to ICL.
Change-Id: I1152d0e882e1acf475072d1553b74f9161e2f485 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/soc/intel/icelake/romstage/romstage.c 1 file changed, 1 insertion(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/32095/1
diff --git a/src/soc/intel/icelake/romstage/romstage.c b/src/soc/intel/icelake/romstage/romstage.c index 92fb1e4..a61370a 100644 --- a/src/soc/intel/icelake/romstage/romstage.c +++ b/src/soc/intel/icelake/romstage/romstage.c @@ -31,8 +31,6 @@ #include <string.h> #include <timestamp.h>
-static struct chipset_power_state power_state; - #define FSP_SMBIOS_MEMORY_INFO_GUID \ { \ 0xd4, 0x71, 0x20, 0x9b, 0x54, 0xb0, 0x0c, 0x4e, \ @@ -111,7 +109,7 @@ bool s3wake; struct postcar_frame pcf; uintptr_t top_of_ram; - struct chipset_power_state *ps = &power_state; + struct chipset_power_state *ps = pmc_get_power_state();
console_init();