Attention is currently required from: Cliff Huang, Jérémy Compostella, Kapil Porwal, Pranava Y N, Ravishankar Sarawadi, Subrata Banik.
Saurabh Mishra has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83635?usp=email )
Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till romstage ......................................................................
Patch Set 73:
(6 comments)
File src/soc/intel/pantherlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/83635/comment/172cc4b0_76eb00d2?usp... : PS64, Line 108: 12
this is correct for PTL-UH […]
Sure, added the PCH details.
File src/soc/intel/pantherlake/chip.h:
https://review.coreboot.org/c/coreboot/+/83635/comment/cd5f40f6_b28d9493?usp... : PS72, Line 63: /* Bit values for use in LpmStateEnableMask. */ : enum lpm_state_mask { : LPM_S0i2_0 = BIT(0), : LPM_S0i2_1 = BIT(1), : LPM_S0i2_2 = BIT(2), : LPM_S0i3_0 = BIT(3), : LPM_S0i3_1 = BIT(4), : LPM_S0i3_2 = BIT(5), : LPM_S0i3_3 = BIT(6), : LPM_S0i3_4 = BIT(7), : LPM_S0iX_ALL = LPM_S0i2_0 | LPM_S0i2_1 | LPM_S0i2_2 : | LPM_S0i3_0 | LPM_S0i3_1 | LPM_S0i3_2 | LPM_S0i3_3 | LPM_S0i3_4, : }; :
do you see any users for these macros ? if not, then please drop
Hi Subrata, we will be using these macros to get supported lpm mask. This later will be used to set a UPD in FSP-S. Keeping the macro.
File src/soc/intel/pantherlake/chipset.cb:
https://review.coreboot.org/c/coreboot/+/83635/comment/61f04481_89b47f87?usp... : PS72, Line 5: PTL_U_H_POWER_LIMITS
as I could see from the doc 823589, […]
Hi Subrata, i have added the corresponding 15W/25W/45W into enum.
Additionally, doc doesn't specify the PL2 value, rather it says that the PL2 is same as ARL-H on same segment. I don't know the PL2 value for ARL as well. Can you please help here. Unable to find PL4 as well in the doc.
I have used the override of Pl2, Pl4 settings from FSP.
File src/soc/intel/pantherlake/include/soc/meminit.h:
https://review.coreboot.org/c/coreboot/+/83635/comment/dc81fbaa_4733b062?usp... : PS72, Line 97: Lp4/
I don't believe we support LP4 with PTL
Acknowledged
File src/soc/intel/pantherlake/include/soc/romstage.h:
https://review.coreboot.org/c/coreboot/+/83635/comment/0439f268_473d157e?usp... : PS72, Line 10: mainboard_update_premem_soc_chip_config
who is the consumer of this code ?
Currently this use is depreciated. Removing.
File src/soc/intel/pantherlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/83635/comment/0dcfc17d_fcd8c0ab?usp... : PS72, Line 26: /*TODO
a space to start with […]
Acknowledged