Attention is currently required from: Dinesh Gehlot, Kapil Porwal, Nick Vaccaro, Subrata Banik, Won Chung.
Hello Dinesh Gehlot, Emilie Roberts, Eric Lai, Kapil Porwal, Nick Vaccaro, Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/81363?usp=email
to look at the new patch set (#3).
Change subject: mb/google/brya: Correct _PLD values ......................................................................
mb/google/brya: Correct _PLD values
For Mithrax and Felwinter, port C1 is on the left side and port C2 is on the right side. Correct the values accordingly.
The board schematics was mirrored, so had to obtain an actual machine and physically check the correct ports.
BUG=b:321051330 TEST=emerge-${BOARD} coreboot then check ACPI table on DUT
Change-Id: I977c3b4081987592a1d46529eb848a07a6c4cb47 Signed-off-by: Won Chung wonchung@google.com --- M src/mainboard/google/brya/variants/felwinter/overridetree.cb M src/mainboard/google/brya/variants/mithrax/overridetree.cb 2 files changed, 10 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/81363/3